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[PATCH v2 4/7] target/riscv: cpu: Add a config option for native debug
From: |
Bin Meng |
Subject: |
[PATCH v2 4/7] target/riscv: cpu: Add a config option for native debug |
Date: |
Sat, 30 Oct 2021 21:55:10 +0800 |
Add a config option to enable support for native M-mode debug.
This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
Changes in v2:
- change the config option to 'disabled' by default
target/riscv/cpu.h | 2 ++
target/riscv/cpu.c | 5 +++++
2 files changed, 7 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1fb13e8b94..b2301425c2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -75,6 +75,7 @@ enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
+ RISCV_FEATURE_DEBUG,
RISCV_FEATURE_MISA
};
@@ -327,6 +328,7 @@ struct RISCVCPU {
bool mmu;
bool pmp;
bool epmp;
+ bool debug;
uint64_t resetvec;
} cfg;
};
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7061ae05fb..84116768ce 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -448,6 +448,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
}
+ if (cpu->cfg.debug) {
+ set_feature(env, RISCV_FEATURE_DEBUG);
+ }
+
set_resetvec(env, cpu->cfg.resetvec);
/* Validate that MISA_MXL is set properly. */
@@ -631,6 +635,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+ DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
--
2.25.1
- [PATCH v2 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs, Bin Meng, 2021/10/30
- [PATCH v2 1/7] target/riscv: Add initial support for native debug, Bin Meng, 2021/10/30
- [PATCH v2 3/7] target/riscv: debug: Implement debug related TCGCPUOps, Bin Meng, 2021/10/30
- [PATCH v2 4/7] target/riscv: cpu: Add a config option for native debug,
Bin Meng <=
- [PATCH v2 2/7] target/riscv: machine: Add debug state description, Bin Meng, 2021/10/30
- [PATCH v2 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint(), Bin Meng, 2021/10/30
- [PATCH v2 5/7] target/riscv: csr: Hook debug CSR read/write, Bin Meng, 2021/10/30
- [PATCH v2 6/7] target/riscv: cpu: Enable native debug feature on virt and sifive_u CPUs, Bin Meng, 2021/10/30