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[PATCH v9 06/76] target/riscv: rvv-1.0: introduce writable misa.v field
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From: |
frank . chang |
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Subject: |
[PATCH v9 06/76] target/riscv: rvv-1.0: introduce writable misa.v field |
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Date: |
Fri, 29 Oct 2021 16:58:11 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Implementations may have a writable misa.v field. Analogous to the way
in which the floating-point unit is handled, the mstatus.vs field may
exist even if misa.v is clear.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 83f4dbd8241..bc149add6ce 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -643,7 +643,7 @@ static RISCVException write_misa(CPURISCVState *env, int
csrno,
val &= env->misa_ext_mask;
/* Mask extensions that are not supported by QEMU */
- val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
/* 'D' depends on 'F', so clear 'D' if 'F' is not present */
if ((val & RVD) && !(val & RVF)) {
--
2.25.1
- [PATCH v9 00/76] support vector extension v1.0, frank . chang, 2021/10/29
- [PATCH v9 01/76] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2021/10/29
- [PATCH v9 02/76] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/10/29
- [PATCH v9 03/76] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2021/10/29
- [PATCH v9 04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty, frank . chang, 2021/10/29
- [PATCH v9 06/76] target/riscv: rvv-1.0: introduce writable misa.v field,
frank . chang <=
- [PATCH v9 05/76] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2021/10/29
- [PATCH v9 07/76] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/10/29
- [PATCH v9 08/76] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/10/29
- [PATCH v9 10/76] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2021/10/29
- [PATCH v9 09/76] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/10/29
- [PATCH v9 11/76] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2021/10/29
- [PATCH v9 12/76] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/10/29
- [PATCH v9 13/76] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2021/10/29
- [PATCH v9 14/76] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2021/10/29
- [PATCH v9 15/76] target/riscv: rvv-1.0: update check functions, frank . chang, 2021/10/29