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Re: [PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode
From: |
Alistair Francis |
Subject: |
Re: [PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function |
Date: |
Tue, 26 Oct 2021 16:30:48 +1000 |
On Fri, Oct 15, 2021 at 6:39 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> helper_set_rounding_mode() is responsible for SIGILL, and "round to odd"
> should be an interface private to translation, so add a new independent
> helper_set_rod_rounding_mode().
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/fpu_helper.c | 5 +++++
> target/riscv/helper.h | 1 +
> target/riscv/internals.h | 1 +
> target/riscv/translate.c | 7 +++++++
> 4 files changed, 14 insertions(+)
>
> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
> index 43ce6148313..cf21097b5fb 100644
> --- a/target/riscv/fpu_helper.c
> +++ b/target/riscv/fpu_helper.c
> @@ -81,6 +81,11 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t
> rm)
> set_float_rounding_mode(softrm, &env->fp_status);
> }
>
> +void helper_set_rod_rounding_mode(CPURISCVState *env)
> +{
> + set_float_rounding_mode(float_round_to_odd, &env->fp_status);
> +}
> +
> static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2,
> uint64_t rs3, int flags)
> {
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 53cf88cd402..606bf72d5cb 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -3,6 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32)
>
> /* Floating Point - rounding mode */
> DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32)
> +DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env)
>
> /* Floating Point - fused */
> DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
> diff --git a/target/riscv/internals.h b/target/riscv/internals.h
> index db105d4d640..065e8162a2f 100644
> --- a/target/riscv/internals.h
> +++ b/target/riscv/internals.h
> @@ -43,6 +43,7 @@ enum {
> RISCV_FRM_RUP = 3, /* Round Up */
> RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
> RISCV_FRM_DYN = 7, /* Dynamic rounding mode */
> + RISCV_FRM_ROD = 8, /* Round to Odd */
> };
>
> static inline uint64_t nanbox_s(float32 f)
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 6a3f105d431..6fa7e016e22 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -30,6 +30,7 @@
> #include "exec/log.h"
>
> #include "instmap.h"
> +#include "internals.h"
>
> /* global register indices */
> static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
> @@ -382,6 +383,12 @@ static void gen_set_rm(DisasContext *ctx, int rm)
> return;
> }
> ctx->frm = rm;
> +
> + if (rm == RISCV_FRM_ROD) {
> + gen_helper_set_rod_rounding_mode(cpu_env);
> + return;
> + }
> +
> gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
> }
>
> --
> 2.25.1
>
>
- [PATCH v8 56/78] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, (continued)
- [PATCH v8 56/78] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2021/10/15
- [PATCH v8 57/78] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 2021/10/15
- [PATCH v8 58/78] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2021/10/15
- [PATCH v8 59/78] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2021/10/15
- [PATCH v8 60/78] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2021/10/15
- [PATCH v8 61/78] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2021/10/15
- [PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/10/15
- [PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/10/15
- Re: [PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function,
Alistair Francis <=
- [PATCH v8 64/78] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/10/15
- [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2021/10/15
- [PATCH v8 66/78] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/10/15
- [PATCH v8 67/78] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/10/15
- [PATCH v8 68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs, frank . chang, 2021/10/15
- [PATCH v8 69/78] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/10/15
- [PATCH v8 70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/10/15
- [PATCH v8 71/78] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/10/15