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[PATCH v17 1/8] target/riscv: Add J-extension into RISC-V
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From: |
Alexey Baturo |
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Subject: |
[PATCH v17 1/8] target/riscv: Add J-extension into RISC-V |
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Date: |
Mon, 25 Oct 2021 20:36:02 +0300 |
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a33dc30be8..1cfc6a53a0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -65,6 +65,7 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
+#define RVJ RV('J')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
@@ -291,6 +292,7 @@ struct RISCVCPU {
bool ext_s;
bool ext_u;
bool ext_h;
+ bool ext_j;
bool ext_v;
bool ext_zba;
bool ext_zbb;
--
2.30.2
- [PATCH v17 0/8] RISC-V Pointer Masking implementation, Alexey Baturo, 2021/10/25
- [PATCH v17 7/8] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension, Alexey Baturo, 2021/10/25
- [PATCH v17 1/8] target/riscv: Add J-extension into RISC-V,
Alexey Baturo <=
- [PATCH v17 4/8] target/riscv: Add J extension state description, Alexey Baturo, 2021/10/25
- [PATCH v17 2/8] target/riscv: Add CSR defines for RISC-V PM extension, Alexey Baturo, 2021/10/25
- [PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode, Alexey Baturo, 2021/10/25
- [PATCH v17 5/8] target/riscv: Print new PM CSRs in QEMU logs, Alexey Baturo, 2021/10/25
- [PATCH v17 6/8] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alexey Baturo, 2021/10/25
- [PATCH v17 8/8] target/riscv: Allow experimental J-ext to be turned on, Alexey Baturo, 2021/10/25