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Re: [PATCH v5 14/16] target/riscv: Align gprs and fprs in cpu_dump
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v5 14/16] target/riscv: Align gprs and fprs in cpu_dump |
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Date: |
Wed, 20 Oct 2021 08:10:37 +1000 |
On Wed, Oct 20, 2021 at 2:18 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Allocate 8 columns per register name.
>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
This probably isn't required though as there is already a similar
patch in my tree:
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4e1920d5f0..f352c2b74c 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -240,7 +240,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
> int flags)
> qemu_fprintf(f, " %s %d\n", "V = ",
> riscv_cpu_virt_enabled(env));
> }
> #endif
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
> + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", "pc", env->pc);
> #ifndef CONFIG_USER_ONLY
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ",
> (target_ulong)env->mstatus);
> @@ -290,15 +290,16 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
> int flags)
> #endif
>
> for (i = 0; i < 32; i++) {
> - qemu_fprintf(f, " %s " TARGET_FMT_lx,
> + qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
> riscv_int_regnames[i], env->gpr[i]);
> if ((i & 3) == 3) {
> qemu_fprintf(f, "\n");
> }
> }
> +
> if (flags & CPU_DUMP_FPU) {
> for (i = 0; i < 32; i++) {
> - qemu_fprintf(f, " %s %016" PRIx64,
> + qemu_fprintf(f, " %-8s %016" PRIx64,
> riscv_fpr_regnames[i], env->fpr[i]);
> if ((i & 3) == 3) {
> qemu_fprintf(f, "\n");
> --
> 2.25.1
>
>
- [PATCH v5 06/16] target/riscv: Use REQUIRE_64BIT in amo_check64, (continued)
- [PATCH v5 06/16] target/riscv: Use REQUIRE_64BIT in amo_check64, Richard Henderson, 2021/10/19
- [PATCH v5 08/16] target/riscv: Replace is_32bit with get_xl/get_xlen, Richard Henderson, 2021/10/19
- [PATCH v5 05/16] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/19
- [PATCH v5 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol, Richard Henderson, 2021/10/19
- [PATCH v5 04/16] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/19
- [PATCH v5 07/16] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/19
- [PATCH v5 10/16] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/19
- [PATCH v5 11/16] target/riscv: Adjust trans_rev8_32 for riscv64, Richard Henderson, 2021/10/19
- [PATCH v5 13/16] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Richard Henderson, 2021/10/19
- [PATCH v5 14/16] target/riscv: Align gprs and fprs in cpu_dump, Richard Henderson, 2021/10/19
- Re: [PATCH v5 14/16] target/riscv: Align gprs and fprs in cpu_dump,
Alistair Francis <=
- [PATCH v5 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump, Richard Henderson, 2021/10/19
- [PATCH v5 12/16] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/19
- [PATCH v5 16/16] target/riscv: Compute mstatus.sd on demand, Richard Henderson, 2021/10/19