Re: [PATCH v4 09/16] target/riscv: Replace DisasContext.w with DisasCont

qemu-riscv

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Re: [PATCH v4 09/16] target/riscv: Replace DisasContext.w with DisasCont

From:	Richard Henderson
Subject:	Re: [PATCH v4 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol
Date:	Mon, 18 Oct 2021 19:30:28 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/18/21 7:24 PM, LIU Zhiwei wrote:

@@ -223,10 +238,15 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num)
  static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
  {
      if (reg_num != 0) {
-        if (ctx->w) {
+        switch (get_ol(ctx)) {
+        case MXL_RV32:
              tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
-        } else {
+            break;
+        case MXL_RV64:
              tcg_gen_mov_tl(cpu_gpr[reg_num], t);
+            break;
+        default:
+            g_assert_not_reached();
          }
      }
  }

The dest_gpr currently will force call gen_set_gpr. However, many cases for MXL_RV64,dest_gpr will return a global TCG variable and don't need to call gen_set_gpr.

In the MXL_RV64 case to which you refer, tcg_gen_mov_tl will be presented with a nop move,and will emit no code. Similarly for TARGET_RISCV32 and the use of tcg_gen_ext32s_tl,which will expand to tcg_gen_mov_i32.

And even x0 can avoid to call gen_set_gpr.  I don't find a good way to utilize 
this point.

You shouldn't special case x0 unless absolutely necessary. We check for it here so thatwe do not have to scatter many checks across the code base.

r~

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[PATCH v4 02/16] target/riscv: Create RISCVMXL enumeration, (continued)
- [PATCH v4 02/16] target/riscv: Create RISCVMXL enumeration, Richard Henderson, 2021/10/18
- [PATCH v4 06/16] target/riscv: Use REQUIRE_64BIT in amo_check64, Richard Henderson, 2021/10/18
- [PATCH v4 05/16] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/18
- [PATCH v4 03/16] target/riscv: Split misa.mxl and misa.ext, Richard Henderson, 2021/10/18
- [PATCH v4 08/16] target/riscv: Replace is_32bit with get_xl/get_xlen, Richard Henderson, 2021/10/18
- [PATCH v4 04/16] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/18
- [PATCH v4 10/16] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/18
- [PATCH v4 07/16] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/18
- [PATCH v4 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol, Richard Henderson, 2021/10/18
  - Re: [PATCH v4 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol, LIU Zhiwei, 2021/10/18
    - Re: [PATCH v4 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol, Richard Henderson <=
- [PATCH v4 12/16] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/18
- [PATCH v4 11/16] target/riscv: Adjust trans_rev8_32 for riscv64, Richard Henderson, 2021/10/18
- [PATCH v4 13/16] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Richard Henderson, 2021/10/18
- [PATCH v4 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump, Richard Henderson, 2021/10/18
  - Re: [PATCH v4 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump, Richard Henderson, 2021/10/18
- [PATCH v4 16/16] target/riscv: Compute mstatus.sd on demand, Richard Henderson, 2021/10/18
- [PATCH v4 14/16] target/riscv: Align gprs and fprs in cpu_dump, Richard Henderson, 2021/10/18
  - Re: [PATCH v4 14/16] target/riscv: Align gprs and fprs in cpu_dump, LIU Zhiwei, 2021/10/18

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