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[PATCH v3 06/14] target/riscv: Use REQUIRE_64BIT in amo_check64
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From: |
Richard Henderson |
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Subject: |
[PATCH v3 06/14] target/riscv: Use REQUIRE_64BIT in amo_check64 |
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Date: |
Sat, 16 Oct 2021 10:14:04 -0700 |
Use the same REQUIRE_64BIT check that we use elsewhere,
rather than open-coding the use of is_32bit.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index fa451938f1..bbc5c93ef1 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -743,7 +743,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
static bool amo_check64(DisasContext *s, arg_rwdvm* a)
{
- return !is_32bit(s) && amo_check(s, a);
+ REQUIRE_64BIT(s);
+ return amo_check(s, a);
}
GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
--
2.25.1
- [PATCH v3 00/14] target/riscv: Rationalize XLEN and operand length, Richard Henderson, 2021/10/16
- [PATCH v3 08/14] target/riscv: Replace is_32bit with get_xl/get_xlen, Richard Henderson, 2021/10/16
- [PATCH v3 05/14] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/16
- [PATCH v3 04/14] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/16
- [PATCH v3 03/14] target/riscv: Split misa.mxl and misa.ext, Richard Henderson, 2021/10/16
- [PATCH v3 06/14] target/riscv: Use REQUIRE_64BIT in amo_check64,
Richard Henderson <=
- [PATCH v3 02/14] target/riscv: Create RISCVMXL enumeration, Richard Henderson, 2021/10/16
- [PATCH v3 01/14] target/riscv: Move cpu_get_tb_cpu_state out of line, Richard Henderson, 2021/10/16
- [PATCH v3 09/14] target/riscv: Replace DisasContext.w with DisasContext.ol, Richard Henderson, 2021/10/16
- [PATCH v3 07/14] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/16
- [PATCH v3 12/14] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/16
- [PATCH v3 11/14] target/riscv: Adjust trans_rev8_32 for riscv64, Richard Henderson, 2021/10/16
- [PATCH v3 10/14] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/16
- [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand, Richard Henderson, 2021/10/16