[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen
|
From: |
Richard Henderson |
|
Subject: |
[PATCH 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen |
|
Date: |
Thu, 7 Oct 2021 10:47:17 -0700 |
In preparation for RV128, replace a simple predicate
with a more versatile test.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 32 +++++++++++++++++---------------
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7e7bb67d15..5724a62bb0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -91,16 +91,18 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
}
#ifdef TARGET_RISCV32
-# define is_32bit(ctx) true
+#define get_xl(ctx) MXL_RV32
#elif defined(CONFIG_USER_ONLY)
-# define is_32bit(ctx) false
+#define get_xl(ctx) MXL_RV64
#else
-static inline bool is_32bit(DisasContext *ctx)
-{
- return ctx->xl == MXL_RV32;
-}
+#define get_xl(ctx) ((ctx)->xl)
#endif
+static inline int get_xlen(DisasContext *ctx)
+{
+ return 16 << get_xl(ctx);
+}
+
/* The word size for this operation. */
static inline int oper_len(DisasContext *ctx)
{
@@ -282,7 +284,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong
imm)
static void mark_fs_dirty(DisasContext *ctx)
{
TCGv tmp;
- target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
+ target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
if (ctx->mstatus_fs != MSTATUS_FS) {
/* Remember the state change for the rest of the TB. */
@@ -341,16 +343,16 @@ EX_SH(12)
} \
} while (0)
-#define REQUIRE_32BIT(ctx) do { \
- if (!is_32bit(ctx)) { \
- return false; \
- } \
+#define REQUIRE_32BIT(ctx) do { \
+ if (get_xl(ctx) != MXL_RV32) { \
+ return false; \
+ } \
} while (0)
-#define REQUIRE_64BIT(ctx) do { \
- if (is_32bit(ctx)) { \
- return false; \
- } \
+#define REQUIRE_64BIT(ctx) do { \
+ if (get_xl(ctx) < MXL_RV64) { \
+ return false; \
+ } \
} while (0)
static int ex_rvc_register(DisasContext *ctx, int reg)
--
2.25.1
- Re: [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line, (continued)
- [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/07
- [PATCH 07/13] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/07
- [PATCH 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Richard Henderson, 2021/10/07
- [PATCH 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/07
- [PATCH 12/13] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/07
- [PATCH 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen,
Richard Henderson <=
- [PATCH 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64, Richard Henderson, 2021/10/07
- [PATCH 03/13] target/riscv: Split misa.mxl and misa.ext, Richard Henderson, 2021/10/07
- [PATCH 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol, Richard Henderson, 2021/10/07
- [PATCH 11/13] target/riscv: Adjust trans_rev8_32 for riscv64, Richard Henderson, 2021/10/07
- [PATCH 10/13] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/07
- Re: [RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length, Frédéric Pétrot, 2021/10/10