Re: [ RFC v2 4/9] target/riscv: Implement mcountinhibit CSR

[Atish Patra]

On Wed, Sep 15, 2021 at 7:54 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, Sep 10, 2021 at 4:29 AM Atish Patra <atish.patra@wdc.com> wrote:
> >
> > As per the privilege specification v1.11, mcountinhibit allows to start/stop
> > a pmu counter selectively.
> >
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> >  target/riscv/cpu.h      |  2 ++
> >  target/riscv/cpu_bits.h |  4 ++++
> >  target/riscv/csr.c      | 25 +++++++++++++++++++++++++
> >  target/riscv/machine.c  |  5 +++--
> >  4 files changed, 34 insertions(+), 2 deletions(-)
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 0e2e88f3bbea..bdb488cdbccc 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -219,6 +219,8 @@ struct CPURISCVState {
> >      target_ulong scounteren;
> >      target_ulong mcounteren;
> >
> > +    target_ulong mcountinhibit;
> > +
> >      target_ulong sscratch;
> >      target_ulong mscratch;
> >
> > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > index 7330ff5a194c..ac519dcdc4df 100644
> > --- a/target/riscv/cpu_bits.h
> > +++ b/target/riscv/cpu_bits.h
> > @@ -275,6 +275,10 @@
> >  #define CSR_MHPMCOUNTER29   0xb1d
> >  #define CSR_MHPMCOUNTER30   0xb1e
> >  #define CSR_MHPMCOUNTER31   0xb1f
> > +
> > +/* Machine counter-inhibit register */
> > +#define CSR_MCOUNTINHIBIT   0x320
> > +
> >  #define CSR_MHPMEVENT3      0x323
> >  #define CSR_MHPMEVENT4      0x324
> >  #define CSR_MHPMEVENT5      0x325
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index fa014bac72ab..a155a4370d6b 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -766,6 +766,28 @@ static RISCVException write_mtvec(CPURISCVState *env, 
> > int csrno,
> >      return RISCV_EXCP_NONE;
> >  }
> >
> > +static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
> > +                                         target_ulong *val)
> > +{
> > +    if (env->priv_ver < PRIV_VERSION_1_11_0) {
> > +        return -RISCV_EXCP_ILLEGAL_INST;
>
> This should be RISCV_EXCP_ILLEGAL_INST
>

Argh. Not sure how this happen :(. My bad.

> > +    }
> > +
> > +    *val = env->mcountinhibit;
> > +    return RISCV_EXCP_NONE;
> > +}
> > +
> > +static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
> > +                                          target_ulong val)
> > +{
> > +    if (env->priv_ver < PRIV_VERSION_1_11_0) {
> > +        return -RISCV_EXCP_ILLEGAL_INST;
>
> ditto
>
> > +    }
> > +
> > +    env->mcountinhibit = val;
> > +    return RISCV_EXCP_NONE;
> > +}
> > +
> >  static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
> >                                        target_ulong *val)
> >  {
> > @@ -1781,6 +1803,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> >      [CSR_MHPMCOUNTER30]  = { "mhpmcounter30",  mctr,   read_zero },
> >      [CSR_MHPMCOUNTER31]  = { "mhpmcounter31",  mctr,   read_zero },
> >
> > +    [CSR_MCOUNTINHIBIT]  = { "mcountinhibi",   any,    read_mcountinhibit,
>
> missing 't' in the register name

Thanks. Will fix it in the next version.

>
> > +                                                       write_mcountinhibit 
> > },
> > +
> >      [CSR_MHPMEVENT3]     = { "mhpmevent3",     any,    read_zero },
> >      [CSR_MHPMEVENT4]     = { "mhpmevent4",     any,    read_zero },
> >      [CSR_MHPMEVENT5]     = { "mhpmevent5",     any,    read_zero },
> > diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> > index 16a08302daff..20dea0843604 100644
> > --- a/target/riscv/machine.c
> > +++ b/target/riscv/machine.c
> > @@ -140,8 +140,8 @@ static const VMStateDescription vmstate_hyper = {
> >
> >  const VMStateDescription vmstate_riscv_cpu = {
> >      .name = "cpu",
> > -    .version_id = 2,
> > -    .minimum_version_id = 2,
> > +    .version_id = 3,
> > +    .minimum_version_id = 3,
> >      .fields = (VMStateField[]) {
> >          VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> >          VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
> > @@ -177,6 +177,7 @@ const VMStateDescription vmstate_riscv_cpu = {
> >          VMSTATE_UINTTL(env.mtval, RISCVCPU),
> >          VMSTATE_UINTTL(env.scounteren, RISCVCPU),
> >          VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
> > +        VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
> >          VMSTATE_UINTTL(env.sscratch, RISCVCPU),
> >          VMSTATE_UINTTL(env.mscratch, RISCVCPU),
> >          VMSTATE_UINT64(env.mfromhost, RISCVCPU),
> > --
>
> Regards,
> Bin
>


-- 
Regards,
Atish