qemu-riscv
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v2 0/4] hw/dma: Align SiFive PDMA behavior with real hardware


From: Frank Chang
Subject: Re: [PATCH v2 0/4] hw/dma: Align SiFive PDMA behavior with real hardware
Date: Sun, 12 Sep 2021 21:05:23 +0800

<frank.chang@sifive.com> 於 2021年9月12日 週日 下午8:46寫道:
From: Frank Chang <frank.chang@sifive.com>

Current QEMU PDMA doesn't align with real PDMA's behavior. This would
result in Linux dmatest failed. This patchest aligns with real PDMA's
behavior we tested on the real board. The golden results are performed
in U-Boot on the Unmatched board with PDMA supported.

Changelog:

v2:
  * Add comment to describe document errors.

Frank Chang (3):
  hw/dma: sifive_pdma: reset Next* registers when Control.claim is set
  hw/dma: sifive_pdma: claim bit must be set before DMA transactions
  hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer

Green Wan (1):
  hw/dma: sifive_pdma: allow non-multiple transaction size transactions

 hw/dma/sifive_pdma.c | 54 +++++++++++++++++++++++++++++++++++---------
 1 file changed, 43 insertions(+), 11 deletions(-)

--
2.25.1



I made a mistake while sending the patchset.
Please ignore this series, I will resend it again.
Sorry for the confusion.

Regards,
Frank Chang 

reply via email to

[Prev in Thread] Current Thread [Next in Thread]