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Re: [PATCH v2 2/3] target/riscv: Implement the stval/mtval illegal instr
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v2 2/3] target/riscv: Implement the stval/mtval illegal instruction |
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Date: |
Wed, 8 Sep 2021 13:53:34 +0800 |
On Wed, Sep 8, 2021 at 12:54 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The stval and mtval registers can optionally contain the faulting
> instruction on an illegal instruction exception. This patch adds support
> for setting the stval and mtval registers based on the CPU feature.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.h | 5 ++++-
> target/riscv/cpu_helper.c | 10 ++++++++++
> target/riscv/translate.c | 31 +++++++++++++++++--------------
> 3 files changed, 31 insertions(+), 15 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[PATCH v2 3/3] target/riscv: Set mtval and stval support, Alistair Francis, 2021/09/08