qemu-riscv
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v1 2/3] hw/riscv/sifive_u: Use the PLIC config helper functio


From: Bin Meng
Subject: Re: [PATCH v1 2/3] hw/riscv/sifive_u: Use the PLIC config helper function
Date: Fri, 3 Sep 2021 19:21:55 +0800

On Fri, Sep 3, 2021 at 2:50 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  include/hw/riscv/virt.h |  1 -
>  hw/riscv/sifive_u.c     | 36 +++++++++++++++++++++++-------------
>  2 files changed, 23 insertions(+), 14 deletions(-)
>
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index 349fee1f89..e95fd15298 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -71,7 +71,6 @@ enum {
>      VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
>  };
>
> -#define VIRT_PLIC_HART_CONFIG "MS"

This does not belong to this patch.

>  #define VIRT_PLIC_NUM_SOURCES 127
>  #define VIRT_PLIC_NUM_PRIORITIES 7
>  #define VIRT_PLIC_PRIORITY_BASE 0x04
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 6cc1a62b0f..9c51b4d052 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -738,6 +738,28 @@ static void sifive_u_machine_init_register_types(void)
>
>  type_init(sifive_u_machine_init_register_types)
>
> +/*
> + * Return the per-socket PLIC hart topology configuration string
> + * (caller must free with g_free())
> + */
> +static char *riscv_plic_hart_config_string(int hart_count)

I think we can create a common helper for all RISC-V machines to use.
The common helper generates the PLIC config string based on misa
feature bit RVS. If RVS is set then the corresponding hart string is
"MS", otherwise "M".

> +{
> +    g_autofree const char **vals = g_new(const char *, hart_count + 1);
> +    int i;
> +
> +    for (i = 0; i < hart_count; i++) {
> +        if (i == 0) {
> +            vals[i] = "M";
> +        } else {
> +            vals[i] = "MS";
> +        }
> +    }
> +    vals[i] = NULL;
> +
> +    /* g_strjoinv() obliges us to cast away const here */
> +    return g_strjoinv(",", (char **)vals);
> +}
> +
>  static void sifive_u_soc_instance_init(Object *obj)
>  {
>      SiFiveUSoCState *s = RISCV_U_SOC(obj);
> @@ -776,7 +798,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error 
> **errp)
>      MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
>      MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
>      char *plic_hart_config;
> -    size_t plic_hart_config_len;
>      int i;
>      NICInfo *nd = &nd_table[0];
>
> @@ -817,18 +838,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error 
> **errp)
>                                  l2lim_mem);
>
>      /* create PLIC hart topology configuration string */
> -    plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
> -                           ms->smp.cpus;
> -    plic_hart_config = g_malloc0(plic_hart_config_len);
> -    for (i = 0; i < ms->smp.cpus; i++) {
> -        if (i != 0) {
> -            strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
> -                    plic_hart_config_len);
> -        } else {
> -            strncat(plic_hart_config, "M", plic_hart_config_len);
> -        }
> -        plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
> -    }
> +    plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
>
>      /* MMIO */
>      s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,

Regards,
Bin



reply via email to

[Prev in Thread] Current Thread [Next in Thread]