[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v5 09/24] target/riscv: Move gen_* helpers for RVM
|
From: |
Richard Henderson |
|
Subject: |
[PATCH v5 09/24] target/riscv: Move gen_* helpers for RVM |
|
Date: |
Mon, 23 Aug 2021 12:55:14 -0700 |
Move these helpers near their use by the trans_*
functions within insn_trans/trans_rvm.c.inc.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 127 ------------------------
target/riscv/insn_trans/trans_rvm.c.inc | 127 ++++++++++++++++++++++++
2 files changed, 127 insertions(+), 127 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1855eacbac..7fbacfa6ee 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -249,133 +249,6 @@ static void gen_set_gpr(DisasContext *ctx, int reg_num,
TCGv t)
}
}
-static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
-{
- TCGv rl = tcg_temp_new();
- TCGv rh = tcg_temp_new();
-
- tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
- /* fix up for one negative */
- tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
- tcg_gen_and_tl(rl, rl, arg2);
- tcg_gen_sub_tl(ret, rh, rl);
-
- tcg_temp_free(rl);
- tcg_temp_free(rh);
-}
-
-static void gen_div(TCGv ret, TCGv source1, TCGv source2)
-{
- TCGv temp1, temp2, zero, one, mone, min;
-
- temp1 = tcg_temp_new();
- temp2 = tcg_temp_new();
- zero = tcg_constant_tl(0);
- one = tcg_constant_tl(1);
- mone = tcg_constant_tl(-1);
- min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
-
- /*
- * If overflow, set temp2 to 1, else source2.
- * This produces the required result of min.
- */
- tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
- tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
- tcg_gen_and_tl(temp1, temp1, temp2);
- tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, source2);
-
- /*
- * If div by zero, set temp1 to -1 and temp2 to 1 to
- * produce the required result of -1.
- */
- tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1);
- tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2);
-
- tcg_gen_div_tl(ret, temp1, temp2);
-
- tcg_temp_free(temp1);
- tcg_temp_free(temp2);
-}
-
-static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
-{
- TCGv temp1, temp2, zero, one, max;
-
- temp1 = tcg_temp_new();
- temp2 = tcg_temp_new();
- zero = tcg_constant_tl(0);
- one = tcg_constant_tl(1);
- max = tcg_constant_tl(~0);
-
- /*
- * If div by zero, set temp1 to max and temp2 to 1 to
- * produce the required result of max.
- */
- tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1);
- tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
- tcg_gen_divu_tl(ret, temp1, temp2);
-
- tcg_temp_free(temp1);
- tcg_temp_free(temp2);
-}
-
-static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
-{
- TCGv temp1, temp2, zero, one, mone, min;
-
- temp1 = tcg_temp_new();
- temp2 = tcg_temp_new();
- zero = tcg_constant_tl(0);
- one = tcg_constant_tl(1);
- mone = tcg_constant_tl(-1);
- min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
-
- /*
- * If overflow, set temp1 to 0, else source1.
- * This avoids a possible host trap, and produces the required result of 0.
- */
- tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
- tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
- tcg_gen_and_tl(temp1, temp1, temp2);
- tcg_gen_movcond_tl(TCG_COND_NE, temp1, temp1, zero, zero, source1);
-
- /*
- * If div by zero, set temp2 to 1, else source2.
- * This avoids a possible host trap, but produces an incorrect result.
- */
- tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
-
- tcg_gen_rem_tl(temp1, temp1, temp2);
-
- /* If div by zero, the required result is the original dividend. */
- tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1);
-
- tcg_temp_free(temp1);
- tcg_temp_free(temp2);
-}
-
-static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
-{
- TCGv temp, zero, one;
-
- temp = tcg_temp_new();
- zero = tcg_constant_tl(0);
- one = tcg_constant_tl(1);
-
- /*
- * If div by zero, set temp to 1, else source2.
- * This avoids a possible host trap, but produces an incorrect result.
- */
- tcg_gen_movcond_tl(TCG_COND_EQ, temp, source2, zero, one, source2);
-
- tcg_gen_remu_tl(temp, source1, temp);
-
- /* If div by zero, the required result is the original dividend. */
- tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp);
-
- tcg_temp_free(temp);
-}
-
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
target_ulong next_pc;
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc
b/target/riscv/insn_trans/trans_rvm.c.inc
index 80552be7a3..b89a85ad3a 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -39,6 +39,21 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
return gen_arith(ctx, a, EXT_NONE, gen_mulh);
}
+static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv rl = tcg_temp_new();
+ TCGv rh = tcg_temp_new();
+
+ tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
+ /* fix up for one negative */
+ tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
+ tcg_gen_and_tl(rl, rl, arg2);
+ tcg_gen_sub_tl(ret, rh, rl);
+
+ tcg_temp_free(rl);
+ tcg_temp_free(rh);
+}
+
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
REQUIRE_EXT(ctx, RVM);
@@ -59,24 +74,136 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
}
+static void gen_div(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv temp1, temp2, zero, one, mone, min;
+
+ temp1 = tcg_temp_new();
+ temp2 = tcg_temp_new();
+ zero = tcg_constant_tl(0);
+ one = tcg_constant_tl(1);
+ mone = tcg_constant_tl(-1);
+ min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
+
+ /*
+ * If overflow, set temp2 to 1, else source2.
+ * This produces the required result of min.
+ */
+ tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
+ tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
+ tcg_gen_and_tl(temp1, temp1, temp2);
+ tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, source2);
+
+ /*
+ * If div by zero, set temp1 to -1 and temp2 to 1 to
+ * produce the required result of -1.
+ */
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2);
+
+ tcg_gen_div_tl(ret, temp1, temp2);
+
+ tcg_temp_free(temp1);
+ tcg_temp_free(temp2);
+}
+
static bool trans_div(DisasContext *ctx, arg_div *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_SIGN, gen_div);
}
+static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv temp1, temp2, zero, one, max;
+
+ temp1 = tcg_temp_new();
+ temp2 = tcg_temp_new();
+ zero = tcg_constant_tl(0);
+ one = tcg_constant_tl(1);
+ max = tcg_constant_tl(~0);
+
+ /*
+ * If div by zero, set temp1 to max and temp2 to 1 to
+ * produce the required result of max.
+ */
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
+ tcg_gen_divu_tl(ret, temp1, temp2);
+
+ tcg_temp_free(temp1);
+ tcg_temp_free(temp2);
+}
+
static bool trans_divu(DisasContext *ctx, arg_divu *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_ZERO, gen_divu);
}
+static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv temp1, temp2, zero, one, mone, min;
+
+ temp1 = tcg_temp_new();
+ temp2 = tcg_temp_new();
+ zero = tcg_constant_tl(0);
+ one = tcg_constant_tl(1);
+ mone = tcg_constant_tl(-1);
+ min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
+
+ /*
+ * If overflow, set temp1 to 0, else source1.
+ * This avoids a possible host trap, and produces the required result of 0.
+ */
+ tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
+ tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
+ tcg_gen_and_tl(temp1, temp1, temp2);
+ tcg_gen_movcond_tl(TCG_COND_NE, temp1, temp1, zero, zero, source1);
+
+ /*
+ * If div by zero, set temp2 to 1, else source2.
+ * This avoids a possible host trap, but produces an incorrect result.
+ */
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
+
+ tcg_gen_rem_tl(temp1, temp1, temp2);
+
+ /* If div by zero, the required result is the original dividend. */
+ tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1);
+
+ tcg_temp_free(temp1);
+ tcg_temp_free(temp2);
+}
+
static bool trans_rem(DisasContext *ctx, arg_rem *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_SIGN, gen_rem);
}
+static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv temp, zero, one;
+
+ temp = tcg_temp_new();
+ zero = tcg_constant_tl(0);
+ one = tcg_constant_tl(1);
+
+ /*
+ * If div by zero, set temp to 1, else source2.
+ * This avoids a possible host trap, but produces an incorrect result.
+ */
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp, source2, zero, one, source2);
+
+ tcg_gen_remu_tl(temp, source1, temp);
+
+ /* If div by zero, the required result is the original dividend. */
+ tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp);
+
+ tcg_temp_free(temp);
+}
+
static bool trans_remu(DisasContext *ctx, arg_remu *a)
{
REQUIRE_EXT(ctx, RVM);
--
2.25.1
- [PATCH v5 00/24] target/riscv: Use tcg_constant_*, Richard Henderson, 2021/08/23
- [PATCH v5 03/24] target/riscv: Clean up division helpers, Richard Henderson, 2021/08/23
- [PATCH v5 02/24] tests/tcg/riscv64: Add test for division, Richard Henderson, 2021/08/23
- [PATCH v5 01/24] target/riscv: Use tcg_constant_*, Richard Henderson, 2021/08/23
- [PATCH v5 05/24] target/riscv: Introduce DisasExtend and new helpers, Richard Henderson, 2021/08/23
- [PATCH v5 04/24] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr, Richard Henderson, 2021/08/23
- [PATCH v5 06/24] target/riscv: Add DisasExtend to gen_arith*, Richard Henderson, 2021/08/23
- [PATCH v5 08/24] target/riscv: Use gen_arith for mulh and mulhu, Richard Henderson, 2021/08/23
- [PATCH v5 07/24] target/riscv: Remove gen_arith_div*, Richard Henderson, 2021/08/23
- [PATCH v5 09/24] target/riscv: Move gen_* helpers for RVM,
Richard Henderson <=
- [PATCH v5 11/24] target/riscv: Add DisasExtend to gen_unary, Richard Henderson, 2021/08/23
- [PATCH v5 10/24] target/riscv: Move gen_* helpers for RVB, Richard Henderson, 2021/08/23
- [PATCH v5 14/24] target/riscv: Use get_gpr in branches, Richard Henderson, 2021/08/23
- [PATCH v5 12/24] target/riscv: Use DisasExtend in shift operations, Richard Henderson, 2021/08/23
- [PATCH v5 16/24] target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation, Richard Henderson, 2021/08/23
- [PATCH v5 13/24] target/riscv: Use extracts for sraiw and srliw, Richard Henderson, 2021/08/23