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Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instruction
From: |
LIU Zhiwei |
Subject: |
Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions |
Date: |
Thu, 12 Aug 2021 06:40:53 +0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 2021/8/12 上午1:56, Richard Henderson
wrote:
On
8/11/21 4:57 AM, LIU Zhiwei wrote:
I still don't know why the value written
sign-extended. If that's the the rule of final specification, I
will try to obey it although our Linux will not depend on the
high part.
The text that I'm looking at is
https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-privileged-20190608.pdf
3.1.6.2 Base ISA Control in mstatus Register
In the fifth paragraph, the requirement for sign-extension is
detailed.
Thanks. I have already seen this rule.
"Whenever XLEN in any mode is set to a value less than the widest supported XLEN, all operations
must ignore source operand register bits above the configured XLEN, and must sign-extend results
to fill the entire widest supported XLEN in the destination register."
I still don't know why the specification has this constraint. It
just requires that fill hardware registers with defined
sign-extension value.
But it doesn't give the real benefit of this constraint.
If the software doesn't use the high part, who cares the really
value in high part? Do you know the benefit? Thanks again.
Best Regards,
Zhiwei
r~
- [RFC PATCH 01/13] target/riscv: Add UXL to tb flags, (continued)
- [RFC PATCH 01/13] target/riscv: Add UXL to tb flags, LIU Zhiwei, 2021/08/04
- [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, LIU Zhiwei, 2021/08/04
- Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, Richard Henderson, 2021/08/05
- Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, LIU Zhiwei, 2021/08/08
- Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, Richard Henderson, 2021/08/09
- Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, LIU Zhiwei, 2021/08/11
- Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, Richard Henderson, 2021/08/11
- Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions,
LIU Zhiwei <=
- Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, Richard Henderson, 2021/08/12
- Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, LIU Zhiwei, 2021/08/12
- Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, Richard Henderson, 2021/08/12
- Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, LIU Zhiwei, 2021/08/12
[RFC PATCH 03/13] target/riscv: Support UXL32 on 64-bit cpu for load/store, LIU Zhiwei, 2021/08/04
[RFC PATCH 04/13] target/riscv: Support UXL32 for slit/sltiu, LIU Zhiwei, 2021/08/04