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[RFC PATCH 10/13] target/riscv: Support UXL32 for float instructions
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From: |
LIU Zhiwei |
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Subject: |
[RFC PATCH 10/13] target/riscv: Support UXL32 for float instructions |
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Date: |
Thu, 5 Aug 2021 10:53:09 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/insn_trans/trans_rvd.c.inc | 4 ++--
target/riscv/insn_trans/trans_rvf.c.inc | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc
b/target/riscv/insn_trans/trans_rvd.c.inc
index 9bb15fdc12..fb033ccd97 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -23,7 +23,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
- TCGv addr = gpr_src(ctx, a->rs1);
+ TCGv addr = gpr_src_u(ctx, a->rs1);
TCGv temp = NULL;
if (a->imm) {
@@ -46,7 +46,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
- TCGv addr = gpr_src(ctx, a->rs1);
+ TCGv addr = gpr_src_u(ctx, a->rs1);
TCGv temp = NULL;
if (a->imm) {
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc
b/target/riscv/insn_trans/trans_rvf.c.inc
index ff8e942199..4576072124 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -28,7 +28,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv addr = gpr_src(ctx, a->rs1);
+ TCGv addr = gpr_src_u(ctx, a->rs1);
TCGv temp = NULL;
if (a->imm) {
@@ -53,7 +53,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv addr = gpr_src(ctx, a->rs1);
+ TCGv addr = gpr_src_u(ctx, a->rs1);
TCGv temp = NULL;
if (a->imm) {
--
2.17.1
- Re: [RFC PATCH 04/13] target/riscv: Support UXL32 for slit/sltiu, (continued)
- [RFC PATCH 05/13] target/riscv: Support UXL32 for shift instruction, LIU Zhiwei, 2021/08/04
- [RFC PATCH 06/13] target/riscv: Fix div instructions, LIU Zhiwei, 2021/08/04
- [RFC PATCH 07/13] target/riscv: Support UXL32 for RVM, LIU Zhiwei, 2021/08/04
- [RFC PATCH 08/13] target/riscv: Support UXL32 for vector instructions, LIU Zhiwei, 2021/08/04
- [RFC PATCH 09/13] target/riscv: Support UXL32 for atomic instructions, LIU Zhiwei, 2021/08/04
- [RFC PATCH 10/13] target/riscv: Support UXL32 for float instructions,
LIU Zhiwei <=
- [RFC PATCH 11/13] target/riscv: Fix srow, LIU Zhiwei, 2021/08/04
- [RFC PATCH 12/13] target/riscv: Support UXL32 for RVB, LIU Zhiwei, 2021/08/04
- [RFC PATCH 13/13] target/riscv: Changing the width of U-mode CSR, LIU Zhiwei, 2021/08/04
- Re: [RFC PATCH 00/13] Support UXL field in mstatus, Alistair Francis, 2021/08/05