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From: | Richard Henderson |
Subject: | Re: [PATCH v1 4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines |
Date: | Fri, 9 Jul 2021 08:41:33 -0700 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 |
On 7/8/21 8:31 PM, Alistair Francis wrote:
switch (mode) { case PLICMode_M: - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level)); + if (level) { + qemu_irq_raise(plic->m_external_irqs[hartid]); + } else { + qemu_irq_lower(plic->m_external_irqs[hartid]); + } break; case PLICMode_S: - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level)); + if (level) { + qemu_irq_raise(plic->s_external_irqs[hartid]); + } else { + qemu_irq_lower(plic->s_external_irqs[hartid]); + } break;
qemu_irq_set. Otherwise, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
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