Re: [PATCH] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned

[Alistair Francis]

On Fri, Jul 9, 2021 at 12:33 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Currently the firmware dynamic info (fw_dyn) is put right after
> the reset vector, which is not 8-byte aligned on RV64. OpenSBI
> fw_dynamic uses ld to read contents from 'struct fw_dynamic_info',
> which expects fw_dyn to be on the 8-byte boundary, otherwise the
> misaligned load exception may happen. Fortunately this does not
> cause any issue on QEMU, as QEMU does support misaligned load.
>
> RV32 does not have any issue as it is 4-byte aligned already.
> Change to make sure it is 8-byte aligned which works for both
> RV32 and RV64.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>
>  hw/riscv/sifive_u.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 273c86418c..4d99566e62 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -599,10 +599,10 @@ static void sifive_u_machine_init(MachineState *machine)
>      }
>
>      /* reset vector */
> -    uint32_t reset_vec[11] = {
> +    uint32_t reset_vec[12] = {
>          s->msel,                       /* MSEL pin state */
>          0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
> -        0x02828613,                    /*     addi   a2, t0, %pcrel_lo(1b) */
> +        0x02c28613,                    /*     addi   a2, t0, %pcrel_lo(1b) */
>          0xf1402573,                    /*     csrr   a0, mhartid  */
>          0,
>          0,
> @@ -610,6 +610,7 @@ static void sifive_u_machine_init(MachineState *machine)
>          start_addr,                    /* start: .dword */
>          start_addr_hi32,
>          fdt_load_addr,                 /* fdt_laddr: .dword */
> +        0x00000000,
>          0x00000000,
>                                         /* fw_dyn: */
>      };
> --
> 2.25.1
>
>