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[PATCH v3 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions
From: |
LIU Zhiwei |
Subject: |
[PATCH v3 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions |
Date: |
Thu, 24 Jun 2021 18:55:08 +0800 |
Q15 saturation is to limit the result to the range
[INT16_MIN, INT16_MAX].
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 8 +++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvp.c.inc | 12 ++++
target/riscv/packed_helper.c | 78 +++++++++++++++++++++++++
4 files changed, 106 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 87a0779842..6ce22a186e 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1361,3 +1361,11 @@ DEF_HELPER_4(smalxds, i64, env, tl, tl, i64)
DEF_HELPER_4(smaldrs, i64, env, tl, tl, i64)
DEF_HELPER_4(smslda, i64, env, tl, tl, i64)
DEF_HELPER_4(smslxda, i64, env, tl, tl, i64)
+
+DEF_HELPER_3(kaddh, tl, env, tl, tl)
+DEF_HELPER_3(ksubh, tl, env, tl, tl)
+DEF_HELPER_3(khmbb, tl, env, tl, tl)
+DEF_HELPER_3(khmbt, tl, env, tl, tl)
+DEF_HELPER_3(khmtt, tl, env, tl, tl)
+DEF_HELPER_3(ukaddh, tl, env, tl, tl)
+DEF_HELPER_3(uksubh, tl, env, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index d1668b34cb..f465851f03 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -964,3 +964,11 @@ smaldrs 1001101 ..... ..... 001 ..... 1110111 @r
smalxds 1010101 ..... ..... 001 ..... 1110111 @r
smslda 1010110 ..... ..... 001 ..... 1110111 @r
smslxda 1011110 ..... ..... 001 ..... 1110111 @r
+
+kaddh 0000010 ..... ..... 001 ..... 1110111 @r
+ksubh 0000011 ..... ..... 001 ..... 1110111 @r
+khmbb 0000110 ..... ..... 001 ..... 1110111 @r
+khmbt 0001110 ..... ..... 001 ..... 1110111 @r
+khmtt 0010110 ..... ..... 001 ..... 1110111 @r
+ukaddh 0001010 ..... ..... 001 ..... 1110111 @r
+uksubh 0001011 ..... ..... 001 ..... 1110111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc
b/target/riscv/insn_trans/trans_rvp.c.inc
index 7c91bdc888..48eb190bc6 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -669,3 +669,15 @@ GEN_RVP_R_D64_ACC_OOL(smaldrs);
GEN_RVP_R_D64_ACC_OOL(smalxds);
GEN_RVP_R_D64_ACC_OOL(smslda);
GEN_RVP_R_D64_ACC_OOL(smslxda);
+
+/*
+ *** Non-SIMD Instructions
+ */
+/* Non-SIMD Q15 saturation ALU Instructions */
+GEN_RVP_R_OOL(kaddh);
+GEN_RVP_R_OOL(ksubh);
+GEN_RVP_R_OOL(khmbb);
+GEN_RVP_R_OOL(khmbt);
+GEN_RVP_R_OOL(khmtt);
+GEN_RVP_R_OOL(ukaddh);
+GEN_RVP_R_OOL(uksubh);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 3330a2ecec..171f88face 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -2526,3 +2526,81 @@ static inline void do_smslxda(CPURISCVState *env, void
*vd, void *va,
}
RVPR64_ACC(smslxda, 2, 2);
+
+/* Q15 saturation instructions */
+static inline void do_kaddh(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int32_t *a = va, *b = vb;
+
+ *d = sat64(env, (int64_t)a[H4(i)] + b[H4(i)], 15);
+}
+
+RVPR(kaddh, 2, 4);
+
+static inline void do_ksubh(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int32_t *a = va, *b = vb;
+
+ *d = sat64(env, (int64_t)a[H4(i)] - b[H4(i)], 15);
+}
+
+RVPR(ksubh, 2, 4);
+
+static inline void do_khmbb(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int16_t *a = va, *b = vb;
+
+ *d = sat64(env, (int64_t)a[H2(i)] * b[H2(i)] >> 15, 15);
+}
+
+RVPR(khmbb, 4, 2);
+
+static inline void do_khmbt(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int16_t *a = va, *b = vb;
+
+ *d = sat64(env, (int64_t)a[H2(i)] * b[H2(i + 1)] >> 15, 15);
+}
+
+RVPR(khmbt, 4, 2);
+
+static inline void do_khmtt(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int16_t *a = va, *b = vb;
+
+ *d = sat64(env, (int64_t)a[H2(i + 1)] * b[H2(i + 1)] >> 15, 15);
+}
+
+RVPR(khmtt, 4, 2);
+
+static inline void do_ukaddh(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ uint32_t *a = va, *b = vb;
+
+ *d = (int16_t)satu64(env, saddu32(env, 0, a[H4(i)], b[H4(i)]), 16);
+}
+
+RVPR(ukaddh, 2, 4);
+
+static inline void do_uksubh(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ uint32_t *a = va, *b = vb;
+
+ *d = (int16_t)satu64(env, ssubu32(env, 0, a[H4(i)], b[H4(i)]), 16);
+}
+
+RVPR(uksubh, 2, 4);
--
2.17.1
- [PATCH v3 14/37] target/riscv: 16-bit Packing Instructions, (continued)
- [PATCH v3 14/37] target/riscv: 16-bit Packing Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 16/37] target/riscv: Signed MSW 32x16 Multiply and Add Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 18/37] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 21/37] target/riscv: 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 22/37] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 23/37] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions,
LIU Zhiwei <=
- [PATCH v3 25/37] target/riscv: Non-SIMD Q31 saturation ALU Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 26/37] target/riscv: 32-bit Computation Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 27/37] target/riscv: Non-SIMD Miscellaneous Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 32/37] target/riscv: RV64 Only 32-bit Multiply Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 34/37] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions, LIU Zhiwei, 2021/06/24