Re: TCG op for 32 bit only cpu on qemu-riscv64

[Richard Henderson]

On 6/6/21 8:07 PM, LIU Zhiwei wrote:
> Hi Alistair,
>
> As I see,  we are moving  on to remove TARGET_RISCV64 macro.
>
> I have some questions:
>
> 1) Which tcg op should use when translate an instruction for 32bit cpu. The 
> tcg_*_i64, tcg_*_i32 or tcg_*_tl?

You use *_tl, because that's the size of the field in CPURISCVState.

> 2) Do we should have a sign-extend 64 bit register(bit 31 as the sign bit)  for 
> 32 bit cpu?

If the value must be sign-extended for RV64, then leave it sign-extended for 
RV32.  There's no point in adding extra code to distinguish between them.

If the instruction does not exist for RV64, then you can probably leave the 
high bits unspecified (sign, zero, or pure garbage).


r~