[PATCH v9 0/6] RISC-V Pointer Masking implementation

[Alexey Baturo]

v9:
Hi folks,

Finaly the J-ext spec has table with preliminary CSR numbers.
Rebased and updated CSR machinery for recent changes.
Addressed Alistair's comments.

v8-resend:
Resending to trigger recheck due to minor codestyle issues.

v8:
Hi folks,

Finally we were able to assign v0.1 draft for Pointer Masking extension for 
RISC-V: 
https://github.com/riscv/riscv-j-extension/blob/master/pointer-masking-proposal.adoc
This is supposed to be the first series of patches with initial support for PM. 
It obviously misses support for hypervisor mode, vector load/stores and some 
other features, while using temporary csr numbers(they're to be assigned by the 
committee a bit later).
With this patch series we were able to run a bunch of tests with HWASAN checks 
enabled.

I hope I've managed to addressed @Alistair's previous comments in this version.

Thanks!

v7:
Hi folks,

Sorry it took me almost 3 month to provide the reply and fixes: it was a really 
busy EOY.
This series contains fixed @Alistair suggestion on enabling J-ext.

As for @Richard comments:
- Indeed I've missed appending review-by to the approved commits. Now I've 
restored them except for the fourth commit. @Richard could you please tell if 
you think it's still ok to commit it as is, or should I support masking mem ops 
for RVV first?
- These patches don't have any support for load/store masking for RVV and RVH 
extensions, so no support for special load/store for Hypervisor in particular.

If this patch series would be accepted, I think my further attention would be 
to:
- Support pm for memory operations for RVV
- Add proper csr and support pm for memory operations for Hypervisor mode
- Support address wrapping on unaligned accesses as @Richard mentioned 
previously

Thanks!

Alexey Baturo (5):
  [RISCV_PM] Add J-extension into RISC-V
  [RISCV_PM] Support CSRs required for RISC-V PM extension except for
    the h-mode
  [RISCV_PM] Print new PM CSRs in QEMU logs
  [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
    instructions
  [RISCV_PM] Allow experimental J-ext to be turned on

Anatoly Parshintsev (1):
  [RISCV_PM] Implement address masking functions required for RISC-V
    Pointer Masking extension

 target/riscv/cpu.c                      |  33 +++
 target/riscv/cpu.h                      |  34 +++
 target/riscv/cpu_bits.h                 |  93 ++++++++
 target/riscv/csr.c                      | 288 ++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rva.c.inc |   3 +
 target/riscv/insn_trans/trans_rvd.c.inc |   2 +
 target/riscv/insn_trans/trans_rvf.c.inc |   2 +
 target/riscv/insn_trans/trans_rvi.c.inc |   2 +
 target/riscv/translate.c                |  42 ++++
 9 files changed, 499 insertions(+)

-- 
2.20.1