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[PATCH v7 02/23] cpu: Restrict target cpu_do_transaction_failed() handle
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v7 02/23] cpu: Restrict target cpu_do_transaction_failed() handlers to sysemu |
Date: |
Mon, 17 May 2021 12:51:19 +0200 |
In commit cbc183d2d9f ("cpu: move cc->transaction_failed to tcg_ops")
we restricted the do_transaction_failed() handler to the sysemu part
of TCGCPUOps, but forgot to restrict the target specific declarations.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/internals.h | 2 ++
target/m68k/cpu.h | 2 ++
target/riscv/cpu.h | 10 +++++-----
target/xtensa/cpu.h | 8 ++++----
4 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 886db56b580..3614f6dd988 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -583,6 +583,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
+#if !defined(CONFIG_USER_ONLY)
/* arm_cpu_do_transaction_failed: handle a memory system error response
* (eg "no device/memory present at address") by raising an external abort
* exception
@@ -592,6 +593,7 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr
physaddr,
MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
+#endif
/* Call any registered EL change hooks */
static inline void arm_call_pre_el_change_hook(ARMCPU *cpu)
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 402c86c8769..cf58fee9ada 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -572,10 +572,12 @@ static inline int cpu_mmu_index (CPUM68KState *env, bool
ifetch)
bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+#if !defined(CONFIG_USER_ONLY)
void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
unsigned size, MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
+#endif
typedef CPUM68KState CPUArchState;
typedef M68kCPU ArchCPU;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0619b491a42..aa19d8f304e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -346,11 +346,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr
addr,
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
-void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
- vaddr addr, unsigned size,
- MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response, uintptr_t retaddr);
char *riscv_isa_string(RISCVCPU *cpu);
void riscv_cpu_list(void);
@@ -359,6 +354,11 @@ void riscv_cpu_list(void);
#define cpu_mmu_index riscv_cpu_mmu_index
#ifndef CONFIG_USER_ONLY
+void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ vaddr addr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 3bd4f691c1a..cbe9e5ff230 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -569,10 +569,6 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
bool probe, uintptr_t retaddr);
void xtensa_cpu_do_interrupt(CPUState *cpu);
bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
-void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr
addr,
- unsigned size, MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response, uintptr_t retaddr);
void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void xtensa_count_regs(const XtensaConfig *config,
@@ -675,6 +671,10 @@ static inline int xtensa_get_cring(const CPUXtensaState
*env)
}
#ifndef CONFIG_USER_ONLY
+void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr
addr,
+ unsigned size, MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size, unsigned *access);
--
2.26.3
- [PATCH v7 00/23] cpu: Introduce SysemuCPUOps structure, Philippe Mathieu-Daudé, 2021/05/17
- [PATCH v7 03/23] cpu: Restrict target cpu_do_unaligned_access() handlers to sysemu, Philippe Mathieu-Daudé, 2021/05/17
- [PATCH v7 04/23] cpu: Remove duplicated 'sysemu/hw_accel.h' header, Philippe Mathieu-Daudé, 2021/05/17
- [PATCH v7 05/23] cpu: Split as cpu-common / cpu-sysemu, Philippe Mathieu-Daudé, 2021/05/17
- [PATCH v7 06/23] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs, Philippe Mathieu-Daudé, 2021/05/17
- [PATCH v7 07/23] cpu: Introduce cpu_virtio_is_big_endian(), Philippe Mathieu-Daudé, 2021/05/17