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[PATCH v8 1/6] [RISCV_PM] Add J-extension into RISC-V
From: |
Alexey Baturo |
Subject: |
[PATCH v8 1/6] [RISCV_PM] Add J-extension into RISC-V |
Date: |
Wed, 28 Apr 2021 01:06:10 +0300 |
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0a33d387ba..0ea9fc65c8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -72,6 +72,7 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
+#define RVJ RV('J')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
@@ -291,6 +292,7 @@ struct RISCVCPU {
bool ext_s;
bool ext_u;
bool ext_h;
+ bool ext_j;
bool ext_v;
bool ext_counters;
bool ext_ifencei;
--
2.20.1
- [PATCH v8 0/6] RISC-V Pointer Masking implementation, Alexey Baturo, 2021/04/27
- [PATCH v8 1/6] [RISCV_PM] Add J-extension into RISC-V,
Alexey Baturo <=
- [PATCH v8 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs, Alexey Baturo, 2021/04/27
- [PATCH v8 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode, Alexey Baturo, 2021/04/27
- [PATCH v8 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alexey Baturo, 2021/04/27
- [PATCH v8 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension, Alexey Baturo, 2021/04/27
- [PATCH v8 6/6] [RISCV_PM] Allow experimental J-ext to be turned on, Alexey Baturo, 2021/04/27
- Re: [PATCH v8 0/6] RISC-V Pointer Masking implementation, no-reply, 2021/04/27