Re: [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

[Alistair Francis]

On Wed, Apr 21, 2021 at 12:17 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/19/21 6:31 PM, frank.chang@sifive.com wrote:
> > From: Frank Chang<frank.chang@sifive.com>
> >
> > In IEEE 754-2008 spec:
> >    Invalid operation exception is signaled when doing:
> >    fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
> >    unless c is a quiet NaN; if c is a quiet NaN then it is
> >    implementation defined whether the invalid operation exception
> >    is signaled.
> >
> > In RISC-V Unprivileged ISA spec:
> >    The fused multiply-add instructions must set the invalid
> >    operation exception flag when the multiplicands are Inf and
> >    zero, even when the addend is a quiet NaN.
> >
> > This commit set invalid operation execption flag for RISC-V when
> > multiplicands of muladd instructions are Inf and zero.
> >
> > Signed-off-by: Frank Chang<frank.chang@sifive.com>
> > ---
> >   fpu/softfloat-specialize.c.inc | 6 ++++++
> >   1 file changed, 6 insertions(+)
> >
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> Alistair, will you take this via your riscv queue?

Yep, getting it now

Alistair

>
>
> r~
>