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[PATCH v2 8/8] target/riscv: Add ePMP support for the Ibex CPU
From: |
Alistair Francis |
Subject: |
[PATCH v2 8/8] target/riscv: Add ePMP support for the Ibex CPU |
Date: |
Fri, 9 Apr 2021 08:20:58 -0400 |
The physical Ibex CPU has ePMP support and it's enabled for the
OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 66787d019c..4bf6a00636 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -202,6 +202,7 @@ static void rv32_ibex_cpu_init(Object *obj)
set_misa(env, RV32 | RVI | RVM | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+ qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
}
static void rv32_imafcu_nommu_cpu_init(Object *obj)
--
2.31.0
- [PATCH v2 0/8] RISC-V: Add support for ePMP v0.9.1, Alistair Francis, 2021/04/09
- [PATCH v2 1/8] target/riscv: Fix the PMP is locked check when using TOR, Alistair Francis, 2021/04/09
- [PATCH v2 3/8] target/riscv: Add the ePMP feature, Alistair Francis, 2021/04/09
- [PATCH v2 4/8] target/riscv: Add ePMP CSR access functions, Alistair Francis, 2021/04/09
- [PATCH v2 2/8] target/riscv: Define ePMP mseccfg, Alistair Francis, 2021/04/09
- [PATCH v2 5/8] target/riscv: Implementation of enhanced PMP (ePMP), Alistair Francis, 2021/04/09
- [PATCH v2 6/8] target/riscv: Add a config option for ePMP, Alistair Francis, 2021/04/09
- [PATCH v2 8/8] target/riscv: Add ePMP support for the Ibex CPU,
Alistair Francis <=
- [PATCH v2 7/8] target/riscv/pmp: Remove outdated comment, Alistair Francis, 2021/04/09