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[PATCH 33/38] target/riscv: RV64 Only 32-bit Multiply Instructions
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From: |
LIU Zhiwei |
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Subject: |
[PATCH 33/38] target/riscv: RV64 Only 32-bit Multiply Instructions |
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Date: |
Fri, 12 Feb 2021 23:02:51 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 3 +++
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn_trans/trans_rvp.c.inc | 4 ++++
target/riscv/packed_helper.c | 19 +++++++++++++++++++
4 files changed, 29 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index f8521a5388..198b010601 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1450,4 +1450,7 @@ DEF_HELPER_3(kdmtt16, tl, env, tl, tl)
DEF_HELPER_4(kdmabb16, tl, env, tl, tl, tl)
DEF_HELPER_4(kdmabt16, tl, env, tl, tl, tl)
DEF_HELPER_4(kdmatt16, tl, env, tl, tl, tl)
+
+DEF_HELPER_3(smbt32, tl, env, tl, tl)
+DEF_HELPER_3(smtt32, tl, env, tl, tl)
#endif
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 2e1c1817e4..46a4e5d080 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -145,3 +145,6 @@ kdmtt16 1111101 ..... ..... 001 ..... 1111111 @r
kdmabb16 1101100 ..... ..... 001 ..... 1111111 @r
kdmabt16 1110100 ..... ..... 001 ..... 1111111 @r
kdmatt16 1111100 ..... ..... 001 ..... 1111111 @r
+
+smbt32 0001100 ..... ..... 010 ..... 1111111 @r
+smtt32 0010100 ..... ..... 010 ..... 1111111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc
b/target/riscv/insn_trans/trans_rvp.c.inc
index 2b4418abd8..33435c3a9e 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -1190,4 +1190,8 @@ GEN_RVP_R_OOL(kdmtt16);
GEN_RVP_R_ACC_OOL(kdmabb16);
GEN_RVP_R_ACC_OOL(kdmabt16);
GEN_RVP_R_ACC_OOL(kdmatt16);
+
+/* (RV64 Only) 32-bit Multiply Instructions */
+GEN_RVP_R_OOL(smbt32);
+GEN_RVP_R_OOL(smtt32);
#endif
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 5636848aaf..11b41637a1 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -3572,5 +3572,24 @@ static inline void do_kdmatt16(CPURISCVState *env, void
*vd, void *va,
RVPR_ACC(kdmatt16, 2, 2);
+/* (RV64 Only) 32-bit Multiply Instructions */
+static inline void do_smbt32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int64_t *d = vd;
+ int32_t *a = va, *b = vb;
+ *d = (int64_t)a[H4(2 * i)] * b[H4(4 * i + 1)];
+}
+
+RVPR(smbt32, 1, sizeof(target_ulong));
+
+static inline void do_smtt32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int64_t *d = vd;
+ int32_t *a = va, *b = vb;
+ *d = (int64_t)a[H4(2 * i + 1)] * b[H4(2 * i + 1)];
+}
+RVPR(smtt32, 1, sizeof(target_ulong));
#endif
--
2.17.1
- [PATCH 23/38] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions, (continued)
- [PATCH 23/38] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 24/38] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 26/38] target/riscv: Non-SIMD Q31 saturation ALU Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 27/38] target/riscv: 32-bit Computation Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 33/38] target/riscv: RV64 Only 32-bit Multiply Instructions,
LIU Zhiwei <=
- [PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 38/38] target/riscv: configure and turn on packed extension from command line, LIU Zhiwei, 2021/02/12