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[PATCH v3 6/9] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal va
From: |
Bin Meng |
Subject: |
[PATCH v3 6/9] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value |
Date: |
Tue, 26 Jan 2021 14:00:04 +0800 |
From: Bin Meng <bin.meng@windriver.com>
All other peripherals' IRQs are in the format of decimal value.
Change SIFIVE_U_GEM_IRQ to be consistent.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
include/hw/riscv/sifive_u.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index de1464a2ce..2656b39808 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -127,7 +127,7 @@ enum {
SIFIVE_U_PDMA_IRQ6 = 29,
SIFIVE_U_PDMA_IRQ7 = 30,
SIFIVE_U_QSPI0_IRQ = 51,
- SIFIVE_U_GEM_IRQ = 0x35
+ SIFIVE_U_GEM_IRQ = 53
};
enum {
--
2.25.1
- [PATCH v3 0/9] hw/riscv: sifive_u: Add missing SPI support, Bin Meng, 2021/01/26
- [PATCH v3 1/9] hw/block: m25p80: Add ISSI SPI flash support, Bin Meng, 2021/01/26
- [PATCH v3 2/9] hw/block: m25p80: Add various ISSI flash information, Bin Meng, 2021/01/26
- [PATCH v3 3/9] hw/ssi: Add SiFive SPI controller support, Bin Meng, 2021/01/26
- [PATCH v3 4/9] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash, Bin Meng, 2021/01/26
- [PATCH v3 5/9] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card, Bin Meng, 2021/01/26
- [PATCH v3 6/9] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value,
Bin Meng <=
- [PATCH v3 7/9] docs/system: Sort targets in alphabetical order, Bin Meng, 2021/01/26
- [PATCH v3 8/9] docs/system: Add RISC-V documentation, Bin Meng, 2021/01/26
- [PATCH v3 9/9] docs/system: riscv: Add documentation for sifive_u machine, Bin Meng, 2021/01/26