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Re: [PATCH v6 20/72] target/riscv: rvv-1.0: fix address index overflow b
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v6 20/72] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns |
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Date: |
Tue, 19 Jan 2021 11:22:31 -0800 |
On Tue, Jan 12, 2021 at 1:57 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Replace ETYPE from signed int to unsigned int to prevent index overflow
> issue, which would lead to wrong index address.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/vector_helper.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 368259f75a0..9349a36b41b 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -361,10 +361,10 @@ static target_ulong NAME(target_ulong base, \
> return (base + *((ETYPE *)vs2 + H(idx))); \
> }
>
> -GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1)
> -GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2)
> -GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4)
> -GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8)
> +GEN_VEXT_GET_INDEX_ADDR(idx_b, uint8_t, H1)
> +GEN_VEXT_GET_INDEX_ADDR(idx_h, uint16_t, H2)
> +GEN_VEXT_GET_INDEX_ADDR(idx_w, uint32_t, H4)
> +GEN_VEXT_GET_INDEX_ADDR(idx_d, uint64_t, H8)
>
> static inline void
> vext_ldst_index(void *vd, void *v0, target_ulong base,
> --
> 2.17.1
>
>
- Re: [PATCH v6 16/72] target/riscv: rvv:1.0: add translation-time nan-box helper function, (continued)
- [PATCH v6 17/72] target/riscv: rvv-1.0: configure instructions, frank . chang, 2021/01/12
- [PATCH v6 18/72] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2021/01/12
- [PATCH v6 19/72] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2021/01/12
- [PATCH v6 21/72] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2021/01/12
- [PATCH v6 20/72] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, frank . chang, 2021/01/12
- Re: [PATCH v6 20/72] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns,
Alistair Francis <=
- [PATCH v6 23/72] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2021/01/12
- [PATCH v6 24/72] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2021/01/12
- [PATCH v6 25/72] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2021/01/12
- [PATCH v6 22/72] target/riscv: rvv-1.0: amo operations, frank . chang, 2021/01/12
- [PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2021/01/12