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Re: [PATCH v6 09/72] target/riscv: rvv-1.0: add vlenb register


From: Alistair Francis
Subject: Re: [PATCH v6 09/72] target/riscv: rvv-1.0: add vlenb register
Date: Tue, 19 Jan 2021 09:39:33 -0800

On Tue, Jan 12, 2021 at 1:40 AM <frank.chang@sifive.com> wrote:
>
> From: Greentime Hu <greentime.hu@sifive.com>
>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_bits.h | 1 +
>  target/riscv/csr.c      | 7 +++++++
>  2 files changed, 8 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 2538580a62a..fcc8fe5cdb4 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -63,6 +63,7 @@
>  #define CSR_VCSR            0x00f
>  #define CSR_VL              0xc20
>  #define CSR_VTYPE           0xc21
> +#define CSR_VLENB           0xc22
>
>  /* VCSR fields */
>  #define VCSR_VXSAT_SHIFT    0
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 4ac1ed8cfa8..7a6554447af 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -272,6 +272,12 @@ static int read_vtype(CPURISCVState *env, int csrno, 
> target_ulong *val)
>      return 0;
>  }
>
> +static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> +    *val = env_archcpu(env)->cfg.vlen >> 3;
> +    return 0;
> +}
> +
>  static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
>  {
>      *val = env->vl;
> @@ -1420,6 +1426,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>      [CSR_VCSR] =                { vs,   read_vcsr,        write_vcsr        
> },
>      [CSR_VL] =                  { vs,   read_vl                             
> },
>      [CSR_VTYPE] =               { vs,   read_vtype                          
> },
> +    [CSR_VLENB] =               { vs,   read_vlenb                          
> },
>      /* User Timers and Counters */
>      [CSR_CYCLE] =               { ctr,  read_instret                        
> },
>      [CSR_INSTRET] =             { ctr,  read_instret                        
> },
> --
> 2.17.1
>
>



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