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[PATCH v6 72/72] target/riscv: set mstatus.SD bit when writing fp CSRs
From: |
frank . chang |
Subject: |
[PATCH v6 72/72] target/riscv: set mstatus.SD bit when writing fp CSRs |
Date: |
Tue, 12 Jan 2021 17:39:46 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/csr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 176010674e8..3baf5c2cf33 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -217,7 +217,7 @@ static int write_fflags(CPURISCVState *env, int csrno,
target_ulong val)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_FS;
+ env->mstatus |= MSTATUS_FS | MSTATUS_SD;
#endif
riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
return 0;
@@ -240,7 +240,7 @@ static int write_frm(CPURISCVState *env, int csrno,
target_ulong val)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_FS;
+ env->mstatus |= MSTATUS_FS | MSTATUS_SD;
#endif
env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
return 0;
@@ -264,7 +264,7 @@ static int write_fcsr(CPURISCVState *env, int csrno,
target_ulong val)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_FS;
+ env->mstatus |= MSTATUS_FS | MSTATUS_SD;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
--
2.17.1
- [PATCH v6 65/72] target/riscv: rvv-1.0: implement vstart CSR, (continued)
- [PATCH v6 65/72] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/01/12
- [PATCH v6 67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs, frank . chang, 2021/01/12
- [PATCH v6 66/72] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/01/12
- [PATCH v6 68/72] target/riscv: gdb: modify gdb csr xml file to align with csr register map, frank . chang, 2021/01/12
- [PATCH v6 69/72] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/01/12
- [PATCH v6 70/72] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/01/12
- [PATCH v6 71/72] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/01/12
- [PATCH v6 72/72] target/riscv: set mstatus.SD bit when writing fp CSRs,
frank . chang <=
- Re: [PATCH v6 00/72] support vector extension v1.0, no-reply, 2021/01/12
- Re: [PATCH v6 00/72] support vector extension v1.0, Alistair Francis, 2021/01/19