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[PATCH v6 36/72] target/riscv: rvv-1.0: floating-point move instruction
From: |
frank . chang |
Subject: |
[PATCH v6 36/72] target/riscv: rvv-1.0: floating-point move instruction |
Date: |
Tue, 12 Jan 2021 17:39:10 +0800 |
From: Frank Chang <frank.chang@sifive.com>
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 1839fc0a56b..7ac7d6a2b92 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2691,9 +2691,15 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f
*a)
require_rvf(s) &&
vext_check_isa_ill(s) &&
require_align(a->rd, s->lmul)) {
+ TCGv_i64 t1;
+
if (s->vl_eq_vlmax) {
+ t1 = tcg_temp_new_i64();
+ /* NaN-box f[rs1] */
+ do_nanbox(s, t1, cpu_fpr[a->rs1]);
+
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
+ MAXSZ(s), MAXSZ(s), t1);
mark_vs_dirty(s);
} else {
TCGv_ptr dest;
@@ -2707,16 +2713,22 @@ static bool trans_vfmv_v_f(DisasContext *s,
arg_vfmv_v_f *a)
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ t1 = tcg_temp_new_i64();
+ /* NaN-box f[rs1] */
+ do_nanbox(s, t1, cpu_fpr[a->rs1]);
+
dest = tcg_temp_new_ptr();
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
+
+ fns[s->sew - 1](dest, t1, cpu_env, desc);
tcg_temp_free_ptr(dest);
tcg_temp_free_i32(desc);
mark_vs_dirty(s);
gen_set_label(over);
}
+ tcg_temp_free_i64(t1);
return true;
}
return false;
--
2.17.1
- [PATCH v6 28/72] target/riscv: rvv-1.0: mask population count instruction, (continued)
- [PATCH v6 28/72] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2021/01/12
- [PATCH v6 29/72] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2021/01/12
- [PATCH v6 30/72] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2021/01/12
- [PATCH v6 31/72] target/riscv: rvv-1.0: iota instruction, frank . chang, 2021/01/12
- [PATCH v6 32/72] target/riscv: rvv-1.0: element index instruction, frank . chang, 2021/01/12
- [PATCH v6 34/72] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2021/01/12
- [PATCH v6 33/72] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2021/01/12
- [PATCH v6 35/72] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2021/01/12
- [PATCH v6 37/72] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2021/01/12
- [PATCH v6 36/72] target/riscv: rvv-1.0: floating-point move instruction,
frank . chang <=
- [PATCH v6 38/72] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2021/01/12
- [PATCH v6 39/72] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2021/01/12
- [PATCH v6 40/72] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2021/01/12
- [PATCH v6 41/72] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2021/01/12
- [PATCH v6 42/72] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2021/01/12
- [PATCH v6 43/72] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2021/01/12
- [PATCH v6 44/72] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2021/01/12
- [PATCH v6 45/72] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2021/01/12
- [PATCH v6 46/72] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2021/01/12