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[PATCH v6 27/72] target/riscv: rvv-1.0: floating-point classify instruct
From: |
frank . chang |
Subject: |
[PATCH v6 27/72] target/riscv: rvv-1.0: floating-point classify instructions |
Date: |
Tue, 12 Jan 2021 17:39:01 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c0053cfb828..a0a47dbceb3 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -561,7 +561,7 @@ vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
-vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm
+vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm
--
2.17.1
- [PATCH v6 23/72] target/riscv: rvv-1.0: load/store whole register instructions, (continued)
- [PATCH v6 23/72] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2021/01/12
- [PATCH v6 24/72] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2021/01/12
- [PATCH v6 25/72] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2021/01/12
- [PATCH v6 22/72] target/riscv: rvv-1.0: amo operations, frank . chang, 2021/01/12
- [PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2021/01/12
- [PATCH v6 27/72] target/riscv: rvv-1.0: floating-point classify instructions,
frank . chang <=
- [PATCH v6 28/72] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2021/01/12
- [PATCH v6 29/72] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2021/01/12
- [PATCH v6 30/72] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2021/01/12
- [PATCH v6 31/72] target/riscv: rvv-1.0: iota instruction, frank . chang, 2021/01/12
- [PATCH v6 32/72] target/riscv: rvv-1.0: element index instruction, frank . chang, 2021/01/12
- [PATCH v6 34/72] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2021/01/12
- [PATCH v6 33/72] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2021/01/12
- [PATCH v6 35/72] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2021/01/12