Re: [PATCH 1/1] hw/riscv: clint: timebase-freq is machine-specific

qemu-riscv

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Re: [PATCH 1/1] hw/riscv: clint: timebase-freq is machine-specific

From:	Palmer Dabbelt
Subject:	Re: [PATCH 1/1] hw/riscv: clint: timebase-freq is machine-specific
Date:	Wed, 25 Nov 2020 17:32:44 -0800 (PST)

On Tue, 03 Nov 2020 07:38:44 PST (-0800), emmanuel.blot@sifive.com wrote:

* sifive_e (HiFive1 platform) uses a RTC clock running at 32.768 KHz
* sifive_u (HiFive Unleashed platform) uses a RTC clock running at 1 MHz


This is a bit oddly done (usually it's sentences as opposed to bullets), but
otherwise

Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>

Thanks!

Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
---
 hw/riscv/sifive_e.c            | 2 +-
 hw/riscv/sifive_u.c            | 4 ++--
 hw/riscv/spike.c               | 4 ++--
 hw/riscv/virt.c                | 4 ++--
 include/hw/intc/sifive_clint.h | 4 ----
 include/hw/riscv/sifive_e.h    | 2 ++
 include/hw/riscv/sifive_u.h    | 2 ++
 include/hw/riscv/spike.h       | 2 ++
 include/hw/riscv/virt.h        | 2 ++
 9 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 59bac4cc9a..89d0fe74b6 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -216,7 +216,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error 
**errp)
     sifive_clint_create(memmap[SIFIVE_E_DEV_CLINT].base,
         memmap[SIFIVE_E_DEV_CLINT].size, 0, ms->smp.cpus,
         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
-        SIFIVE_CLINT_TIMEBASE_FREQ, false);
+        SIFIVE_E_CLINT_TIMEBASE_FREQ, false);
     create_unimplemented_device("riscv.sifive.e.aon",
         memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size);
     sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b2472c6627..403f614eca 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -155,7 +155,7 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,

     qemu_fdt_add_subnode(fdt, "/cpus");
     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
-        SIFIVE_CLINT_TIMEBASE_FREQ);
+        SIFIVE_U_CLINT_TIMEBASE_FREQ);
     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);

@@ -739,7 +739,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error 
**errp)
     sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
         memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
-        SIFIVE_CLINT_TIMEBASE_FREQ, false);
+        SIFIVE_U_CLINT_TIMEBASE_FREQ, false);

     if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
         return;
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index facac6e7d2..4beeeb4ef6 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -98,7 +98,7 @@ static void create_fdt(SpikeState *s, const struct 
MemmapEntry *memmap,

     qemu_fdt_add_subnode(fdt, "/cpus");
     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
-        SIFIVE_CLINT_TIMEBASE_FREQ);
+        SPIKE_CLINT_TIMEBASE_FREQ);
     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
     qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
@@ -244,7 +244,7 @@ static void spike_board_init(MachineState *machine)
             memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
             memmap[SPIKE_CLINT].size, base_hartid, hart_count,
             SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
-            SIFIVE_CLINT_TIMEBASE_FREQ, false);
+            SPIKE_CLINT_TIMEBASE_FREQ, false);
     }

     /* register system main memory (actual RAM) */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 6bfd10dfc7..837368696c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -213,7 +213,7 @@ static void create_fdt(RISCVVirtState *s, const struct 
MemmapEntry *memmap,

     qemu_fdt_add_subnode(fdt, "/cpus");
     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
-                          SIFIVE_CLINT_TIMEBASE_FREQ);
+                          VIRT_CLINT_TIMEBASE_FREQ);
     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
     qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
@@ -543,7 +543,7 @@ static void virt_machine_init(MachineState *machine)
             memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
             memmap[VIRT_CLINT].size, base_hartid, hart_count,
             SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
-            SIFIVE_CLINT_TIMEBASE_FREQ, true);
+            VIRT_CLINT_TIMEBASE_FREQ, true);

         /* Per-socket PLIC hart topology configuration string */
         plic_hart_config_len =
diff --git a/include/hw/intc/sifive_clint.h b/include/hw/intc/sifive_clint.h
index a30be0f3d6..04856fd04b 100644
--- a/include/hw/intc/sifive_clint.h
+++ b/include/hw/intc/sifive_clint.h
@@ -53,8 +53,4 @@ enum {
     SIFIVE_TIME_BASE    = 0xBFF8
 };

-enum {
-    SIFIVE_CLINT_TIMEBASE_FREQ = 10000000
-};
-
 #endif
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 83604da805..dbaba7f205 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -80,6 +80,8 @@ enum {
     SIFIVE_E_GPIO0_IRQ0 = 8
 };

+#define SIFIVE_E_CLINT_TIMEBASE_FREQ 32768
+
 #define SIFIVE_E_PLIC_HART_CONFIG "M"
 #define SIFIVE_E_PLIC_NUM_SOURCES 127
 #define SIFIVE_E_PLIC_NUM_PRIORITIES 7
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index a9f7b4a084..dcdc708799 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -137,6 +137,8 @@ enum {
 #define SIFIVE_U_MANAGEMENT_CPU_COUNT   1
 #define SIFIVE_U_COMPUTE_CPU_COUNT      4

+#define SIFIVE_U_CLINT_TIMEBASE_FREQ 1000000
+
 #define SIFIVE_U_PLIC_HART_CONFIG "MS"
 #define SIFIVE_U_PLIC_NUM_SOURCES 54
 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index cddeca2e77..d131bf4091 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -53,4 +53,6 @@ enum {
 #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
 #endif

+#define SPIKE_CLINT_TIMEBASE_FREQ 10000000
+
 #endif
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index b4ed9a32eb..d9e417852a 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -70,6 +70,8 @@ enum {
     VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
 };

+#define VIRT_CLINT_TIMEBASE_FREQ 10000000
+
 #define VIRT_PLIC_HART_CONFIG "MS"
 #define VIRT_PLIC_NUM_SOURCES 127
 #define VIRT_PLIC_NUM_PRIORITIES 7

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[PATCH 0/1] CLINT timebase frequency is invalid for sifive machines, Emmanuel Blot, 2020/11/03
- [PATCH 1/1] hw/riscv: clint: timebase-freq is machine-specific, Emmanuel Blot, 2020/11/03
  - Re: [PATCH 1/1] hw/riscv: clint: timebase-freq is machine-specific, Palmer Dabbelt <=
- Re: [PATCH 0/1] CLINT timebase frequency is invalid for sifive machines, Emmanuel Blot, 2020/11/16

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