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[PATCH v2 07/10] hw/riscv: microchip_pfsoc: Connect the SYSREG module
From: |
Bin Meng |
Subject: |
[PATCH v2 07/10] hw/riscv: microchip_pfsoc: Connect the SYSREG module |
Date: |
Wed, 28 Oct 2020 13:30:07 +0800 |
From: Bin Meng <bin.meng@windriver.com>
Previously SYSREG was created as an unimplemented device. Now that
we have a simple SYSREG module, connect it.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
hw/riscv/Kconfig | 1 +
hw/riscv/microchip_pfsoc.c | 9 ++++++---
include/hw/riscv/microchip_pfsoc.h | 2 ++
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 8f043e3..facb0cb 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -7,6 +7,7 @@ config MICROCHIP_PFSOC
select MCHP_PFSOC_DMC
select MCHP_PFSOC_IOSCB
select MCHP_PFSOC_MMUART
+ select MCHP_PFSOC_SYSREG
select MSI_NONBROKEN
select SIFIVE_CLINT
select SIFIVE_PDMA
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 438e0c4..bc908e0 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -153,6 +153,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma-controller", &s->dma,
TYPE_SIFIVE_PDMA);
+ object_initialize_child(obj, "sysreg", &s->sysreg,
+ TYPE_MCHP_PFSOC_SYSREG);
+
object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
@@ -280,9 +283,9 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
Error **errp)
}
/* SYSREG */
- create_unimplemented_device("microchip.pfsoc.sysreg",
- memmap[MICROCHIP_PFSOC_SYSREG].base,
- memmap[MICROCHIP_PFSOC_SYSREG].size);
+ sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
+ memmap[MICROCHIP_PFSOC_SYSREG].base);
/* MPUCFG */
create_unimplemented_device("microchip.pfsoc.mpucfg",
diff --git a/include/hw/riscv/microchip_pfsoc.h
b/include/hw/riscv/microchip_pfsoc.h
index a244ae6..245c82d 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -26,6 +26,7 @@
#include "hw/dma/sifive_pdma.h"
#include "hw/misc/mchp_pfsoc_dmc.h"
#include "hw/misc/mchp_pfsoc_ioscb.h"
+#include "hw/misc/mchp_pfsoc_sysreg.h"
#include "hw/net/cadence_gem.h"
#include "hw/sd/cadence_sdhci.h"
@@ -47,6 +48,7 @@ typedef struct MicrochipPFSoCState {
MchpPfSoCMMUartState *serial2;
MchpPfSoCMMUartState *serial3;
MchpPfSoCMMUartState *serial4;
+ MchpPfSoCSysregState sysreg;
SiFivePDMAState dma;
CadenceGEMState gem0;
CadenceGEMState gem1;
--
2.7.4
- [PATCH v2 00/10] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box, Bin Meng, 2020/10/28
- [PATCH v2 01/10] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps, Bin Meng, 2020/10/28
- [PATCH v2 02/10] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support, Bin Meng, 2020/10/28
- [PATCH v2 03/10] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules, Bin Meng, 2020/10/28
- [PATCH v2 04/10] hw/misc: Add Microchip PolarFire SoC IOSCB module support, Bin Meng, 2020/10/28
- [PATCH v2 06/10] hw/misc: Add Microchip PolarFire SoC SYSREG module support, Bin Meng, 2020/10/28
- [PATCH v2 05/10] hw/riscv: microchip_pfsoc: Connect the IOSCB module, Bin Meng, 2020/10/28
- [PATCH v2 07/10] hw/riscv: microchip_pfsoc: Connect the SYSREG module,
Bin Meng <=
- [PATCH v2 08/10] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0, Bin Meng, 2020/10/28
- [PATCH v2 09/10] hw/riscv: microchip_pfsoc: Correct DDR memory map, Bin Meng, 2020/10/28
- [PATCH v2 10/10] hw/riscv: microchip_pfsoc: Hook the I2C1 controller, Bin Meng, 2020/10/28
- Re: [PATCH v2 00/10] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box, Alistair Francis, 2020/10/28