[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v1 1/5] target/riscv: Add a virtualised MMU Mode
|
From: |
Alistair Francis |
|
Subject: |
Re: [PATCH v1 1/5] target/riscv: Add a virtualised MMU Mode |
|
Date: |
Fri, 23 Oct 2020 16:29:52 -0700 |
On Fri, Oct 23, 2020 at 12:13 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 10/23/20 8:26 AM, Alistair Francis wrote:
> > +++ b/target/riscv/cpu-param.h
> > @@ -18,6 +18,6 @@
> > # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
> > #endif
> > #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
> > -#define NB_MMU_MODES 4
> > +#define NB_MMU_MODES 8
>
> Is there really a PRV_M + virt enabled state?
No, there isn't.
>
> > +#define TB_FLAGS_PRIV_MMU_MASK 3
> ...
> > - int mode = mmu_idx;
> > + int mode = mmu_idx & 0x3;
>
> Use that MASK here?
Good idea.
Alistair
>
>
> r~
- [PATCH v1 0/5] Fix the Hypervisor access functions, Alistair Francis, 2020/10/23
- [PATCH v1 1/5] target/riscv: Add a virtualised MMU Mode, Alistair Francis, 2020/10/23
- [PATCH v1 2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses, Alistair Francis, 2020/10/23
- [PATCH v1 3/5] target/riscv: Remove the HS_TWO_STAGE flag, Alistair Francis, 2020/10/23
- [PATCH v1 4/5] target/riscv: Remove the hyp load and store functions, Alistair Francis, 2020/10/23
- [PATCH v1 5/5] target/riscv: Split the Hypervisor execute load helpers, Alistair Francis, 2020/10/23