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RE: [PATCH V3 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into o
From: |
Jiangyifei |
Subject: |
RE: [PATCH V3 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit |
Date: |
Fri, 23 Oct 2020 09:41:08 +0000 |
> -----Original Message-----
> From: Jiangyifei
> Sent: Friday, October 23, 2020 5:12 PM
> To: qemu-devel@nongnu.org; qemu-riscv@nongnu.org
> Cc: palmer@dabbelt.com; Alistair.Francis@wdc.com;
> sagark@eecs.berkeley.edu; kbastian@mail.uni-paderborn.de;
> richard.henderson@linaro.org; Zhangxiaofeng (F)
> <victor.zhangxiaofeng@huawei.com>; Wubin (H) <wu.wubin@huawei.com>;
> Zhanghailiang <zhang.zhanghailiang@huawei.com>; dengkai (A)
> <dengkai1@huawei.com>; yinyipeng <yinyipeng1@huawei.com>; Jiangyifei
> <jiangyifei@huawei.com>
> Subject: [PATCH V3 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into
> one uint64_t unit
>
> mstatus/mstatush and vsstatus/vsstatush are two halved for RISCV32.
> This patch expands mstatus and vsstatus to uint64_t instead of target_ulong
> so that it can be saved as one unit and reduce some ifdefs in the code.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> ---
......
> static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
> {
> - if ((val ^ env->mstatush) & (MSTATUS_MPV)) {
> + uint64_t valh = (uint64_t)val << 32;
> + uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
> +
> + if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
> tlb_flush(env_cpu(env));
> }
>
> - val &= MSTATUS_MPV | MSTATUS_GVA;
> -
> - env->mstatush = val;
> + env->mstatus = (env->mstatus & ~mask) | (valh & mask);
>
> return 0;
> }
Hi Alistair,
It's a little different here.
Previously, except for MPV and GVA, other bits were cleared.
Now, except for MPV and GVA, other bits are reserved.
Refer to write_mstatus () and specification, I think it's better now.
How does it sound?
Yifei
- Re: [PATCH V3 2/6] target/riscv: Add basic vmstate description of CPU, (continued)
- [PATCH V3 4/6] target/riscv: Add H extension state description, Yifei Jiang, 2020/10/23
- [PATCH V3 5/6] target/riscv: Add V extension state description, Yifei Jiang, 2020/10/23
- [PATCH V3 6/6] target/riscv: Add sifive_plic vmstate, Yifei Jiang, 2020/10/23
- [PATCH V3 3/6] target/riscv: Add PMP state description, Yifei Jiang, 2020/10/23
- [PATCH V3 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit, Yifei Jiang, 2020/10/23