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[PATCH v5 0/6] RISC-V Pointer Masking implementation
From: |
Alexey Baturo |
Subject: |
[PATCH v5 0/6] RISC-V Pointer Masking implementation |
Date: |
Thu, 22 Oct 2020 10:43:03 +0300 |
Hi,
Addressing Alistair comment: J-ext enabling patch is now the last one in the
series.
Thanks
Alexey Baturo (5):
[RISCV_PM] Add J-extension into RISC-V
[RISCV_PM] Support CSRs required for RISC-V PM extension except for
ones in hypervisor mode
[RISCV_PM] Print new PM CSRs in QEMU logs
[RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
instructions
[RISCV_PM] Allow experimental J-ext to be turned on
Anatoly Parshintsev (1):
[RISCV_PM] Implement address masking functions required for RISC-V
Pointer Masking extension
target/riscv/cpu.c | 30 +++
target/riscv/cpu.h | 33 +++
target/riscv/cpu_bits.h | 66 ++++++
target/riscv/csr.c | 271 ++++++++++++++++++++++++
target/riscv/insn_trans/trans_rva.c.inc | 3 +
target/riscv/insn_trans/trans_rvd.c.inc | 2 +
target/riscv/insn_trans/trans_rvf.c.inc | 2 +
target/riscv/insn_trans/trans_rvi.c.inc | 2 +
target/riscv/translate.c | 44 ++++
9 files changed, 453 insertions(+)
--
2.20.1
- [PATCH v5 0/6] RISC-V Pointer Masking implementation,
Alexey Baturo <=
- [PATCH v5 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alexey Baturo, 2020/10/22
- [PATCH v5 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode, Alexey Baturo, 2020/10/22
- [PATCH v5 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension, Alexey Baturo, 2020/10/22
- [PATCH v5 6/6] [RISCV_PM] Allow experimental J-ext to be turned on, Alexey Baturo, 2020/10/22
- [PATCH v5 1/6] [RISCV_PM] Add J-extension into RISC-V, Alexey Baturo, 2020/10/22
- [PATCH v5 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs, Alexey Baturo, 2020/10/22
- Re: [PATCH v5 0/6] RISC-V Pointer Masking implementation, no-reply, 2020/10/22