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[RFC v5 26/68] target/riscv: rvv-1.0: floating-point square-root instruc
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From: |
frank . chang |
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Subject: |
[RFC v5 26/68] target/riscv: rvv-1.0: floating-point square-root instruction |
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Date: |
Wed, 30 Sep 2020 03:04:01 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 44d35c0271..6c95a3460a 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -538,7 +538,7 @@ vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
-vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm
+vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
--
2.17.1
- [RFC v5 16/68] target/riscv: rvv:1.0: add translation-time nan-box helper function, (continued)
- [RFC v5 16/68] target/riscv: rvv:1.0: add translation-time nan-box helper function, frank . chang, 2020/09/29
- [RFC v5 17/68] target/riscv: rvv-1.0: configure instructions, frank . chang, 2020/09/29
- [RFC v5 18/68] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2020/09/29
- [RFC v5 19/68] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2020/09/29
- [RFC v5 20/68] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/09/29
- [RFC v5 21/68] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2020/09/29
- [RFC v5 22/68] target/riscv: rvv-1.0: amo operations, frank . chang, 2020/09/29
- [RFC v5 23/68] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2020/09/29
- [RFC v5 24/68] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2020/09/29
- [RFC v5 25/68] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2020/09/29
- [RFC v5 26/68] target/riscv: rvv-1.0: floating-point square-root instruction,
frank . chang <=
- [RFC v5 27/68] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2020/09/29
- [RFC v5 28/68] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2020/09/29
- [RFC v5 29/68] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2020/09/29
- [RFC v5 30/68] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2020/09/29
- [RFC v5 31/68] target/riscv: rvv-1.0: iota instruction, frank . chang, 2020/09/29
- [RFC v5 32/68] target/riscv: rvv-1.0: element index instruction, frank . chang, 2020/09/29
- [RFC v5 33/68] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2020/09/29
- [RFC v5 34/68] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2020/09/29
- [RFC v5 35/68] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2020/09/29
- [RFC v5 36/68] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2020/09/29