[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [RFC v4 36/70] target/riscv: rvv-1.0: floating-point move instructio
From: |
Richard Henderson |
Subject: |
Re: [RFC v4 36/70] target/riscv: rvv-1.0: floating-point move instruction |
Date: |
Sat, 29 Aug 2020 13:00:59 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 8/17/20 1:49 AM, frank.chang@sifive.com wrote:
> static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
> {
> if (require_rvv(s) &&
> + has_ext(s, RVF) &&
> vext_check_isa_ill(s) &&
> require_align(a->rd, 1 << s->lmul) &&
> (s->sew != 0)) {
> + TCGv_i64 t1 = tcg_temp_local_new_i64();
> + /* NaN-box f[rs1] */
> + do_nanbox(s, t1, cpu_fpr[a->rs1]);
Don't you need to check
s->sew == MO_64 ? has_ext(s, RVD) : has_ext(s, RVF)
?
It might be worth folding that into it's own helper function, which also
incorporates the s->sew != 0 check. E.g.
static bool require_rvf(Disascontext *s)
{
switch (s->sew) {
case MO_16:
case MO_32:
return has_ext(s, RVF);
case MO_64:
return has_ext(s, RVD);
default:
return false;
}
}
> + TCGv_i64 t1 = tcg_temp_local_new_i64();
> + /* NaN-box f[rs1] */
> + do_nanbox(s, t1, cpu_fpr[a->rs1]);
> +
> if (s->vl_eq_vlmax) {
> tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
> - MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
> + MAXSZ(s), MAXSZ(s), t1);
> mark_vs_dirty(s);
> } else {
> TCGv_ptr dest;
Recall that local temps get written to the stack at branches.
You should avoid the local temp by computing do_nanbox on both arms of this IF.
In the else branch, do_nanbox should be after the brcond.
r~
- [RFC v4 28/70] target/riscv: rvv-1.0: mask population count instruction, (continued)
- [RFC v4 28/70] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2020/08/17
- [RFC v4 29/70] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2020/08/17
- [RFC v4 30/70] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2020/08/17
- [RFC v4 31/70] target/riscv: rvv-1.0: iota instruction, frank . chang, 2020/08/17
- [RFC v4 32/70] target/riscv: rvv-1.0: element index instruction, frank . chang, 2020/08/17
- [RFC v4 33/70] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2020/08/17
- [RFC v4 34/70] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2020/08/17
- [RFC v4 35/70] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2020/08/17
- [RFC v4 36/70] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2020/08/17
- Re: [RFC v4 36/70] target/riscv: rvv-1.0: floating-point move instruction,
Richard Henderson <=
- [RFC v4 37/70] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2020/08/17
- [RFC v4 38/70] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2020/08/17
- [RFC v4 39/70] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2020/08/17
- [RFC v4 40/70] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2020/08/17
- [RFC v4 41/70] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2020/08/17
- [RFC v4 43/70] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2020/08/17