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[RFC v4 70/70] target/riscv: gdb: support vector registers for rv32
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From: |
frank . chang |
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Subject: |
[RFC v4 70/70] target/riscv: gdb: support vector registers for rv32 |
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Date: |
Mon, 17 Aug 2020 16:49:55 +0800 |
From: Greentime Hu <greentime.hu@sifive.com>
This patch adds vector support for rv32 gdb. It allows gdb client to access
vector registers correctly.
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
gdb-xml/riscv-32bit-csr.xml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml
index 3d2031da7dc..bb98b927995 100644
--- a/gdb-xml/riscv-32bit-csr.xml
+++ b/gdb-xml/riscv-32bit-csr.xml
@@ -248,4 +248,11 @@
<reg name="mucounteren" bitsize="32"/>
<reg name="mscounteren" bitsize="32"/>
<reg name="mhcounteren" bitsize="32"/>
+ <reg name="vstart" bitsize="32" group="vector"/>
+ <reg name="vxsat" bitsize="32" group="vector"/>
+ <reg name="vxrm" bitsize="32" group="vector"/>
+ <reg name="vcsr" bitsize="32" group="vector"/>
+ <reg name="vl" bitsize="32" group="vector"/>
+ <reg name="vtype" bitsize="32" group="vector"/>
+ <reg name="vlenb" bitsize="32" group="vector"/>
</feature>
--
2.17.1
- [RFC v4 65/70] target/riscv: add "set round to odd" rounding mode helper function, (continued)
- [RFC v4 65/70] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2020/08/17
- [RFC v4 66/70] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2020/08/17
- [RFC v4 67/70] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 512-bits, frank . chang, 2020/08/17
- [RFC v4 68/70] target/riscv: gdb: modify gdb csr xml file to align with csr register map, frank . chang, 2020/08/17
- [RFC v4 69/70] target/riscv: gdb: support vector registers for rv64, frank . chang, 2020/08/17
- [RFC v4 70/70] target/riscv: gdb: support vector registers for rv32,
frank . chang <=
- Re: [RFC v4 00/70] support vector extension v1.0, Frank Chang, 2020/08/25