Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support

[Anup Patel]

On Fri, Aug 14, 2020 at 10:12 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This adds support for Microchip PolarFire SoC Icicle Kit board.
> The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
> E51 plus four U54 cores and many on-chip peripherals and an FPGA.

Nice Work !!! This is very helpful.

>
> For more details about Microchip PolarFire Soc, please see:
> https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
>
> The Icicle Kit board information can be found here:
> https://www.microsemi.com/existing-parts/parts/152514
>
> Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000.
> The RISC-V CPU and HART codes has been updated to set the core's
> reset vector based on a configurable property from machine codes.
>
> The following perepherals are created as an unimplemented device:
>
> - Bus Error Uint 0/1/2/3/4
> - L2 cache controller
> - SYSREG
> - MPUCFG
> - IOSCBCFG
> - GPIO
>
> The following perepherals are emulated:
> - SiFive CLINT
> - SiFive PLIC
> - PolarFire SoC Multi-Mode UART
> - PolarFire SoC DMA
> - Cadence eMMC/SDHCI controller
> - Cadence Gigabit Ethernet MAC
>
> Some bugs in the SD card codes are fixed during the development.
>
> The BIOS image used by this machine is hss.bin, aka Hart Software
> Services, which can be built from:
> https://github.com/polarfire-soc/hart-software-services
>
> To launch this machine:
> $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
>     -bios path/to/hss.bin -sd path/to/sdcard.img \
>     -nic tap,ifname=tap,script=no,model=cadence_gem \
>     -display none -serial stdio \
>     -chardev socket,id=serial1,path=serial1.sock,server,wait \
>     -serial chardev:serial1

Currently, it is fine to use HSS (with OpenSBI v0.6 as a library) but
this is not aligned with the existing booting flow of many RISC-V
systems.

It will be nice to have standard U-Boot RISC-V boot-flow working
on Microchip PolarFire SoC:
U-Boot SPL (BIOS) => FW_DYNAMIC (Generic) => U-Boot S-mode

The Microchip HSS is quite convoluted. It has:
1. DDR Init
2. Boot device support
3. SBI support using OpenSBI as library
4. Simple TEE support

I think point 1) and 2) above should be part of U-Boot SPL.
The point 3) can be OpenSBI FW_DYNAMIC.

Lastly,for point 4), we are working on a new OpenSBI feature using
which we can run independent Secure OS and Non-Secure OS using
U-Boot_SPL+OpenSBI (for both SiFive Unleashed and Microchip
PolarFire).

Do you have plans for adding U-Boot SPL support for this board ??

Regards,
Anup

>
> The memory is set to 1 GiB by default to match the hardware.
> A sanity check on ram size is performed in the machine init routine
> to prompt user to increase the RAM size to > 1 GiB when less than
> 1 GiB ram is detected.
>
> HSS output is on the first serial port (stdio) and U-Boot/Linux
> outputs on the 2nd serial port. OpenSBI outputs on a random serial
> port due to the lottery mechanism used during the multi-core boot.
>
>
> Bin Meng (18):
>   target/riscv: cpu: Add a new 'resetvec' property
>   hw/riscv: hart: Add a new 'resetvec' property
>   target/riscv: cpu: Set reset vector based on the configured property
>     value
>   hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
>   hw/char: Add Microchip PolarFire SoC MMUART emulation
>   hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
>   hw/sd: sd: Fix incorrect populated function switch status data
>     structure
>   hw/sd: sd: Correctly set the high capacity bit
>   hw/sd: sdhci: Make sdhci_poweron_reset() internal visible
>   hw/sd: Add Cadence SDHCI emulation
>   hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an
>     SD card
>   hw/dma: Add Microchip PolarFire Soc DMA controller emulation
>   hw/riscv: microchip_pfsoc: Connect a DMA controller
>   hw/net: cadence_gem: Add a new 'phy-addr' property
>   hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
>   hw/riscv: microchip_pfsoc: Hook GPIO controllers
>   hw/riscv: clint: Avoid using hard-coded timebase frequency
>   hw/riscv: microchip_pfsoc: Document the software used for testing
>
>  MAINTAINERS                         |  11 +
>  default-configs/riscv64-softmmu.mak |   1 +
>  hw/char/Kconfig                     |   3 +
>  hw/char/Makefile.objs               |   1 +
>  hw/char/mchp_pfsoc_mmuart.c         |  82 +++++++
>  hw/dma/Kconfig                      |   3 +
>  hw/dma/Makefile.objs                |   1 +
>  hw/dma/mchp_pfsoc_dma.c             | 322 +++++++++++++++++++++++++
>  hw/net/cadence_gem.c                |   7 +-
>  hw/riscv/Kconfig                    |   9 +
>  hw/riscv/Makefile.objs              |   1 +
>  hw/riscv/microchip_pfsoc.c          | 456 
> ++++++++++++++++++++++++++++++++++++
>  hw/riscv/opentitan.c                |   1 +
>  hw/riscv/riscv_hart.c               |   3 +
>  hw/riscv/sifive_clint.c             |  25 +-
>  hw/riscv/sifive_e.c                 |   4 +-
>  hw/riscv/sifive_u.c                 |   5 +-
>  hw/riscv/spike.c                    |   2 +-
>  hw/riscv/virt.c                     |   3 +-
>  hw/sd/Kconfig                       |   4 +
>  hw/sd/Makefile.objs                 |   1 +
>  hw/sd/cadence_sdhci.c               | 162 +++++++++++++
>  hw/sd/sd.c                          |   8 +-
>  hw/sd/sdhci-internal.h              |   1 +
>  hw/sd/sdhci.c                       |   2 +-
>  include/hw/char/mchp_pfsoc_mmuart.h |  61 +++++
>  include/hw/dma/mchp_pfsoc_dma.h     |  57 +++++
>  include/hw/net/cadence_gem.h        |   2 +
>  include/hw/riscv/microchip_pfsoc.h  | 125 ++++++++++
>  include/hw/riscv/riscv_hart.h       |   1 +
>  include/hw/riscv/sifive_clint.h     |   3 +-
>  include/hw/sd/cadence_sdhci.h       |  65 +++++
>  target/riscv/cpu.c                  |   8 +-
>  target/riscv/cpu.h                  |   7 +-
>  target/riscv/cpu_helper.c           |   4 +-
>  target/riscv/csr.c                  |   4 +-
>  36 files changed, 1424 insertions(+), 31 deletions(-)
>  create mode 100644 hw/char/mchp_pfsoc_mmuart.c
>  create mode 100644 hw/dma/mchp_pfsoc_dma.c
>  create mode 100644 hw/riscv/microchip_pfsoc.c
>  create mode 100644 hw/sd/cadence_sdhci.c
>  create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
>  create mode 100644 include/hw/dma/mchp_pfsoc_dma.h
>  create mode 100644 include/hw/riscv/microchip_pfsoc.h
>  create mode 100644 include/hw/sd/cadence_sdhci.h
>
> --
> 2.7.4
>
>