Re: [PATCH 1/3] softfloat: target/riscv: implement full set fp16 comparision

[Alistair Francis]

On Thu, Jul 30, 2020 at 2:54 AM Chih-Min Chao <chihmin.chao@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Implement them in softfloat and remove local version in riscv
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
> Acked-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  include/fpu/softfloat.h      | 41 +++++++++++++++++++++++++++++++++++++++++
>  target/riscv/vector_helper.c | 25 -------------------------
>  2 files changed, 41 insertions(+), 25 deletions(-)
>
> diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
> index 659218b..573fce9 100644
> --- a/include/fpu/softfloat.h
> +++ b/include/fpu/softfloat.h
> @@ -285,6 +285,47 @@ static inline float16 float16_set_sign(float16 a, int 
> sign)
>      return make_float16((float16_val(a) & 0x7fff) | (sign << 15));
>  }
>
> +static inline bool float16_eq(float16 a, float16 b, float_status *s)
> +{
> +    return float16_compare(a, b, s) == float_relation_equal;
> +}
> +
> +static inline bool float16_le(float16 a, float16 b, float_status *s)
> +{
> +    return float16_compare(a, b, s) <= float_relation_equal;
> +}
> +
> +static inline bool float16_lt(float16 a, float16 b, float_status *s)
> +{
> +    return float16_compare(a, b, s) < float_relation_equal;
> +}
> +
> +static inline bool float16_unordered(float16 a, float16 b, float_status *s)
> +{
> +    return float16_compare(a, b, s) == float_relation_unordered;
> +}
> +
> +static inline bool float16_eq_quiet(float16 a, float16 b, float_status *s)
> +{
> +    return float16_compare_quiet(a, b, s) == float_relation_equal;
> +}
> +
> +static inline bool float16_le_quiet(float16 a, float16 b, float_status *s)
> +{
> +    return float16_compare_quiet(a, b, s) <= float_relation_equal;
> +}
> +
> +static inline bool float16_lt_quiet(float16 a, float16 b, float_status *s)
> +{
> +    return float16_compare_quiet(a, b, s) < float_relation_equal;
> +}
> +
> +static inline bool float16_unordered_quiet(float16 a, float16 b,
> +                                           float_status *s)
> +{
> +    return float16_compare_quiet(a, b, s) == float_relation_unordered;
> +}
> +
>  #define float16_zero make_float16(0)
>  #define float16_half make_float16(0x3800)
>  #define float16_one make_float16(0x3c00)
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 39f44d1..c68e6c4 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -3955,12 +3955,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void 
> *vs2,   \
>      }                                                         \
>  }
>
> -static bool float16_eq_quiet(uint16_t a, uint16_t b, float_status *s)
> -{
> -    FloatRelation compare = float16_compare_quiet(a, b, s);
> -    return compare == float_relation_equal;
> -}
> -
>  GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet)
>  GEN_VEXT_CMP_VV_ENV(vmfeq_vv_w, uint32_t, H4, float32_eq_quiet)
>  GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet)
> @@ -4017,12 +4011,6 @@ GEN_VEXT_CMP_VF(vmfne_vf_h, uint16_t, H2, vmfne16)
>  GEN_VEXT_CMP_VF(vmfne_vf_w, uint32_t, H4, vmfne32)
>  GEN_VEXT_CMP_VF(vmfne_vf_d, uint64_t, H8, vmfne64)
>
> -static bool float16_lt(uint16_t a, uint16_t b, float_status *s)
> -{
> -    FloatRelation compare = float16_compare(a, b, s);
> -    return compare == float_relation_less;
> -}
> -
>  GEN_VEXT_CMP_VV_ENV(vmflt_vv_h, uint16_t, H2, float16_lt)
>  GEN_VEXT_CMP_VV_ENV(vmflt_vv_w, uint32_t, H4, float32_lt)
>  GEN_VEXT_CMP_VV_ENV(vmflt_vv_d, uint64_t, H8, float64_lt)
> @@ -4030,13 +4018,6 @@ GEN_VEXT_CMP_VF(vmflt_vf_h, uint16_t, H2, float16_lt)
>  GEN_VEXT_CMP_VF(vmflt_vf_w, uint32_t, H4, float32_lt)
>  GEN_VEXT_CMP_VF(vmflt_vf_d, uint64_t, H8, float64_lt)
>
> -static bool float16_le(uint16_t a, uint16_t b, float_status *s)
> -{
> -    FloatRelation compare = float16_compare(a, b, s);
> -    return compare == float_relation_less ||
> -           compare == float_relation_equal;
> -}
> -
>  GEN_VEXT_CMP_VV_ENV(vmfle_vv_h, uint16_t, H2, float16_le)
>  GEN_VEXT_CMP_VV_ENV(vmfle_vv_w, uint32_t, H4, float32_le)
>  GEN_VEXT_CMP_VV_ENV(vmfle_vv_d, uint64_t, H8, float64_le)
> @@ -4091,12 +4072,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16)
>  GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32)
>  GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64)
>
> -static bool float16_unordered_quiet(uint16_t a, uint16_t b, float_status *s)
> -{
> -    FloatRelation compare = float16_compare_quiet(a, b, s);
> -    return compare == float_relation_unordered;
> -}
> -
>  GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet)
>  GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet)
>  GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet)
> --
> 2.7.4
>
>