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Re: [RFC 13/65] target/riscv: rvv-0.9: configure instructions
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From: |
Richard Henderson |
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Subject: |
Re: [RFC 13/65] target/riscv: rvv-0.9: configure instructions |
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Date: |
Fri, 10 Jul 2020 11:06:57 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 |
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> -static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
> +static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a)
Do not mix this change with anything else.
> + rd = tcg_const_i32(a->rd);
> + rs1 = tcg_const_i32(a->rs1);
Any time you put a register number into a tcg const, there's probably a better
way to do things.
> - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
> - if (a->rs1 == 0) {
> - /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
> - s1 = tcg_const_tl(RV_VLEN_MAX);
> - } else {
> - s1 = tcg_temp_new();
> - gen_get_gpr(s1, a->rs1);
> - }
E.g. this code should be kept, and add
if (a->rd == 0 && a->rs1 == 0) {
s1 = tcg_temp_new();
tcg_gen_mov_tl(s1, cpu_vl);
} else ...
> + if ((sew > cpu->cfg.elen)
> + || vill
> + || vflmul < ((float)sew / cpu->cfg.elen)
> + || (ediv != 0)
> + || (reserved != 0)) {
> /* only set vill bit. */
> env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
> - env->vl = 0;
> - env->vstart = 0;
> return 0;
> }
You do need to check 0.7.1 so long as it's supported.
r~
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, (continued)
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Richard Henderson, 2020/07/10
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/13
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, LIU Zhiwei, 2020/07/13
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/14
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Richard Henderson, 2020/07/14
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/14
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, LIU Zhiwei, 2020/07/14
[RFC 09/65] target/riscv: rvv-0.9: add vlenb register, frank . chang, 2020/07/10
[RFC 13/65] target/riscv: rvv-0.9: configure instructions, frank . chang, 2020/07/10
- Re: [RFC 13/65] target/riscv: rvv-0.9: configure instructions,
Richard Henderson <=
[RFC 15/65] target/riscv: rvv-0.9: index load and store instructions, frank . chang, 2020/07/10
[RFC 20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns, frank . chang, 2020/07/10
[RFC 21/65] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation, frank . chang, 2020/07/10
[RFC 22/65] target/riscv: rvv-0.9: floating-point square-root instruction, frank . chang, 2020/07/10
[RFC 28/65] target/riscv: rvv-0.9: element index instruction, frank . chang, 2020/07/10
[RFC 32/65] target/riscv: rvv-0.9: integer extension instructions, frank . chang, 2020/07/10
[RFC 33/65] target/riscv: rvv-0.9: single-width averaging add and subtract instructions, frank . chang, 2020/07/10
[RFC 35/65] target/riscv: rvv-0.9: narrowing integer right shift instructions, frank . chang, 2020/07/10
[RFC 38/65] target/riscv: rvv-0.9: integer merge and move instructions, frank . chang, 2020/07/10