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Re: [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL p


From: Alistair Francis
Subject: Re: [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state
Date: Mon, 15 Jun 2020 09:41:19 -0700

On Mon, Jun 8, 2020 at 7:27 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> On SiFive FU540 SoC, the value stored at physical address 0x1000
> stores the MSEL pin state that is used to control the next boot
> location that ROM codes jump to.
>
> Add a new property msel to sifive_u machine for this.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  hw/riscv/sifive_u.c         | 7 +++++++
>  include/hw/riscv/sifive_u.h | 1 +
>  2 files changed, 8 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 07e2ba0..aaa5adb 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -507,6 +507,13 @@ static void sifive_u_machine_instance_init(Object *obj)
>                                      "Set on to tell QEMU's ROM to jump to "
>                                      "flash. Otherwise QEMU will jump to 
> DRAM");
>
> +    s->msel = 0;
> +    object_property_add(obj, "msel", "uint32",
> +                        sifive_u_machine_get_uint32_prop,
> +                        sifive_u_machine_set_uint32_prop, NULL, &s->msel);
> +    object_property_set_description(obj, "msel",
> +                                    "Mode Select (MSEL[3:0]) pin state");
> +
>      s->serial = OTP_SERIAL;
>      object_property_add(obj, "serial", "uint32",
>                          sifive_u_machine_get_uint32_prop,
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index dcf7f3b..d82cfe0 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -63,6 +63,7 @@ typedef struct SiFiveUState {
>      int fdt_size;
>
>      bool start_in_flash;
> +    uint32_t msel;
>      uint32_t serial;
>  } SiFiveUState;
>
> --
> 2.7.4
>
>



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