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Re: [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP |
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Date: |
Mon, 15 Jun 2020 09:08:13 -0700 |
On Mon, Jun 8, 2020 at 7:21 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Upstream U-Boot v2020.07 codes switch to access SiFive FU540 OTP
> based on device tree information. Let's generate the device tree
> node for OTP.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index cf7f833..8dc6842 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -207,6 +207,17 @@ static void create_fdt(SiFiveUState *s, const struct
> MemmapEntry *memmap,
> g_free(cells);
> g_free(nodename);
>
> + nodename = g_strdup_printf("/soc/otp@%lx",
> + (long)memmap[SIFIVE_U_OTP].base);
> + qemu_fdt_add_subnode(fdt, nodename);
> + qemu_fdt_setprop_cell(fdt, nodename, "fuse-count",
> SIFIVE_U_OTP_REG_SIZE);
> + qemu_fdt_setprop_cells(fdt, nodename, "reg",
> + 0x0, memmap[SIFIVE_U_OTP].base,
> + 0x0, memmap[SIFIVE_U_OTP].size);
> + qemu_fdt_setprop_string(fdt, nodename, "compatible",
> + "sifive,fu540-c000-otp");
> + g_free(nodename);
> +
> prci_phandle = phandle++;
> nodename = g_strdup_printf("/soc/clock-controller@%lx",
> (long)memmap[SIFIVE_U_PRCI].base);
> --
> 2.7.4
>
>
- [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support, Bin Meng, 2020/06/08
- [PATCH 02/15] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions, Bin Meng, 2020/06/08
- [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions, Bin Meng, 2020/06/08
- [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP, Bin Meng, 2020/06/08
- Re: [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP,
Alistair Francis <=
- [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit, Bin Meng, 2020/06/08
- [PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs, Bin Meng, 2020/06/08
- [PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes, Bin Meng, 2020/06/08
- [PATCH 06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property, Bin Meng, 2020/06/08
- [PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller, Bin Meng, 2020/06/08