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[PATCH v2 12/17] target/riscv: Update the CSRs to the v0.6 Hyp extension
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From: |
Alistair Francis |
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Subject: |
[PATCH v2 12/17] target/riscv: Update the CSRs to the v0.6 Hyp extension |
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Date: |
Thu, 4 Jun 2020 18:21:15 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 6b97c27711..8a145e0a32 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -422,15 +422,17 @@
#endif
/* hstatus CSR bits */
-#define HSTATUS_SPRV 0x00000001
+#define HSTATUS_VSBE 0x00000020
+#define HSTATUS_GVA 0x00000040
#define HSTATUS_SPV 0x00000080
-#define HSTATUS_SP2P 0x00000100
-#define HSTATUS_SP2V 0x00000200
+#define HSTATUS_SPVP 0x00000100
+#define HSTATUS_HU 0x00000200
+#define HSTATUS_VGEIN 0x0003F000
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTSR 0x00400000
-#define HSTATUS_HU 0x00000200
-#define HSTATUS_GVA 0x00000040
-#define HSTATUS_SPVP 0x00000100
+#if defined(TARGET_RISCV64)
+#define HSTATUS_VSXL 0x300000000
+#endif
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
--
2.26.2
- [PATCH v2 01/17] target/riscv: Set access as data_load when validating stage-2 PTEs, (continued)
- [PATCH v2 01/17] target/riscv: Set access as data_load when validating stage-2 PTEs, Alistair Francis, 2020/06/04
- [PATCH v2 02/17] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/06/04
- [PATCH v2 03/17] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/06/04
- [PATCH v2 04/17] target/riscv: Implement checks for hfence, Alistair Francis, 2020/06/04
- [PATCH v2 05/17] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/06/04
- [PATCH v2 11/17] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/06/04
- [PATCH v2 12/17] target/riscv: Update the CSRs to the v0.6 Hyp extension,
Alistair Francis <=
- [PATCH v2 07/17] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/06/04
- [PATCH v2 06/17] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/06/04
- [PATCH v2 08/17] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/06/04
- [PATCH v2 09/17] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/06/04
- [PATCH v2 13/17] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/06/04
- [PATCH v2 10/17] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/06/04
- [PATCH v2 14/17] target/riscv: Only support little endian guests, Alistair Francis, 2020/06/04
- [PATCH v2 15/17] target/riscv: Support the v0.6 Hypervisor extension CRSs, Alistair Francis, 2020/06/04
- [PATCH v2 16/17] target/riscv: Return the exception from invalid CSR accesses, Alistair Francis, 2020/06/04
- [PATCH v2 17/17] target/riscv: Support the Virtual Instruction fault, Alistair Francis, 2020/06/04