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Re: [PATCH v8 42/62] target/riscv: vector floating-point merge instructi
From: |
Alistair Francis |
Subject: |
Re: [PATCH v8 42/62] target/riscv: vector floating-point merge instructions |
Date: |
Fri, 29 May 2020 13:36:40 -0700 |
On Thu, May 21, 2020 at 4:09 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/helper.h | 4 +++
> target/riscv/insn32.decode | 2 ++
> target/riscv/insn_trans/trans_rvv.inc.c | 38 +++++++++++++++++++++++++
> target/riscv/vector_helper.c | 24 ++++++++++++++++
> 4 files changed, 68 insertions(+)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 23b268df90..21054cc957 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -994,3 +994,7 @@ DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env,
> i32)
> DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32)
> DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32)
> DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32)
> +
> +DEF_HELPER_6(vfmerge_vfm_h, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfmerge_vfm_w, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfmerge_vfm_d, void, ptr, ptr, i64, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 23e80fe954..14cb4e2e66 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -513,6 +513,8 @@ vmfge_vf 011111 . ..... ..... 101 ..... 1010111
> @r_vm
> vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
> vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
> vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm
> +vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
> +vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
>
> vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
> vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
> b/target/riscv/insn_trans/trans_rvv.inc.c
> index 621220e5ff..dfa2177331 100644
> --- a/target/riscv/insn_trans/trans_rvv.inc.c
> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> @@ -2177,3 +2177,41 @@ GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
>
> /* Vector Floating-Point Classify Instruction */
> GEN_OPFV_TRANS(vfclass_v, opfv_check)
> +
> +/* Vector Floating-Point Merge Instruction */
> +GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
> +
> +static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
> +{
> + if (vext_check_isa_ill(s) &&
> + vext_check_reg(s, a->rd, false) &&
> + (s->sew != 0)) {
> +
> + if (s->vl_eq_vlmax) {
> + tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
> + MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
> + } else {
> + TCGv_ptr dest;
> + TCGv_i32 desc;
> + uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
> + static gen_helper_vmv_vx * const fns[3] = {
> + gen_helper_vmv_v_x_h,
> + gen_helper_vmv_v_x_w,
> + gen_helper_vmv_v_x_d,
> + };
> + TCGLabel *over = gen_new_label();
> + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
> +
> + dest = tcg_temp_new_ptr();
> + desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
> + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
> + fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
> +
> + tcg_temp_free_ptr(dest);
> + tcg_temp_free_i32(desc);
> + gen_set_label(over);
> + }
> + return true;
> + }
> + return false;
> +}
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 63d8873c0a..018293570d 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4193,3 +4193,27 @@ RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d)
> GEN_VEXT_V(vfclass_v_h, 2, 2, clearh)
> GEN_VEXT_V(vfclass_v_w, 4, 4, clearl)
> GEN_VEXT_V(vfclass_v_d, 8, 8, clearq)
> +
> +/* Vector Floating-Point Merge Instruction */
> +#define GEN_VFMERGE_VF(NAME, ETYPE, H, CLEAR_FN) \
> +void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
> + CPURISCVState *env, uint32_t desc) \
> +{ \
> + uint32_t mlen = vext_mlen(desc); \
> + uint32_t vm = vext_vm(desc); \
> + uint32_t vl = env->vl; \
> + uint32_t esz = sizeof(ETYPE); \
> + uint32_t vlmax = vext_maxsz(desc) / esz; \
> + uint32_t i; \
> + \
> + for (i = 0; i < vl; i++) { \
> + ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
> + *((ETYPE *)vd + H(i)) \
> + = (!vm && !vext_elem_mask(v0, mlen, i) ? s2 : s1); \
> + } \
> + CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
> +}
> +
> +GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2, clearh)
> +GEN_VFMERGE_VF(vfmerge_vfm_w, int32_t, H4, clearl)
> +GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8, clearq)
> --
> 2.23.0
>
>
- [PATCH v8 34/62] target/riscv: vector widening floating-point multiply, (continued)
- [PATCH v8 34/62] target/riscv: vector widening floating-point multiply, LIU Zhiwei, 2020/05/21
- [PATCH v8 35/62] target/riscv: vector single-width floating-point fused multiply-add instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 36/62] target/riscv: vector widening floating-point fused multiply-add instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 37/62] target/riscv: vector floating-point square-root instruction, LIU Zhiwei, 2020/05/21
- [PATCH v8 38/62] target/riscv: vector floating-point min/max instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 39/62] target/riscv: vector floating-point sign-injection instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 40/62] target/riscv: vector floating-point compare instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 41/62] target/riscv: vector floating-point classify instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 42/62] target/riscv: vector floating-point merge instructions, LIU Zhiwei, 2020/05/21
- Re: [PATCH v8 42/62] target/riscv: vector floating-point merge instructions,
Alistair Francis <=
- [PATCH v8 43/62] target/riscv: vector floating-point/integer type-convert instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 44/62] target/riscv: widening floating-point/integer type-convert instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 45/62] target/riscv: narrowing floating-point/integer type-convert instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 46/62] target/riscv: vector single-width integer reduction instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 47/62] target/riscv: vector wideing integer reduction instructions, LIU Zhiwei, 2020/05/21