[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v5 01/11] riscv/boot: Add a missing header include
|
From: |
Alistair Francis |
|
Subject: |
[PATCH v5 01/11] riscv/boot: Add a missing header include |
|
Date: |
Thu, 28 May 2020 15:14:09 -0700 |
As the functions declared in this header use the symbol_fn_t
typedef itself declared in "hw/loader.h", we need to include
it here to make the header file self-contained.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
---
include/hw/riscv/boot.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 474a940ad5..9daa98da08 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -21,6 +21,7 @@
#define RISCV_BOOT_H
#include "exec/cpu-defs.h"
+#include "hw/loader.h"
void riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
--
2.26.2
- [PATCH v5 00/11] RISC-V Add the OpenTitan Machine, Alistair Francis, 2020/05/28
- [PATCH v5 02/11] target/riscv: Don't overwrite the reset vector, Alistair Francis, 2020/05/28
- [PATCH v5 01/11] riscv/boot: Add a missing header include,
Alistair Francis <=
- [PATCH v5 03/11] target/riscv: Disable the MMU correctly, Alistair Francis, 2020/05/28
- [PATCH v5 04/11] target/riscv: Don't set PMP feature in the cpu init, Alistair Francis, 2020/05/28
- [PATCH v5 05/11] target/riscv: Add the lowRISC Ibex CPU, Alistair Francis, 2020/05/28
- [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine, Alistair Francis, 2020/05/28
- [PATCH v5 11/11] target/riscv: Use a smaller guess size for no-MMU PMP, Alistair Francis, 2020/05/28
- [PATCH v5 08/11] hw/intc: Initial commit of lowRISC Ibex PLIC, Alistair Francis, 2020/05/28
- [PATCH v5 09/11] riscv/opentitan: Connect the PLIC device, Alistair Francis, 2020/05/28
- [PATCH v5 07/11] hw/char: Initial commit of Ibex UART, Alistair Francis, 2020/05/28
- [PATCH v5 10/11] riscv/opentitan: Connect the UART device, Alistair Francis, 2020/05/28