[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v5 02/11] target/riscv: Don't overwrite the reset vector
From: |
Alistair Francis |
Subject: |
[PATCH v5 02/11] target/riscv: Don't overwrite the reset vector |
Date: |
Thu, 28 May 2020 15:14:12 -0700 |
The reset vector is set in the init function don't set it again in
realize.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 059d71f2c7..5eb3c02735 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -133,6 +133,7 @@ static void riscv_base32_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, 0);
+ set_resetvec(env, DEFAULT_RSTVEC);
}
static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
@@ -180,6 +181,7 @@ static void riscv_base64_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, 0);
+ set_resetvec(env, DEFAULT_RSTVEC);
}
static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
@@ -399,7 +401,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
set_priv_version(env, priv_version);
- set_resetvec(env, DEFAULT_RSTVEC);
if (cpu->cfg.mmu) {
set_feature(env, RISCV_FEATURE_MMU);
--
2.26.2
- [PATCH v5 00/11] RISC-V Add the OpenTitan Machine, Alistair Francis, 2020/05/28
- [PATCH v5 02/11] target/riscv: Don't overwrite the reset vector,
Alistair Francis <=
- [PATCH v5 01/11] riscv/boot: Add a missing header include, Alistair Francis, 2020/05/28
- [PATCH v5 03/11] target/riscv: Disable the MMU correctly, Alistair Francis, 2020/05/28
- [PATCH v5 04/11] target/riscv: Don't set PMP feature in the cpu init, Alistair Francis, 2020/05/28
- [PATCH v5 05/11] target/riscv: Add the lowRISC Ibex CPU, Alistair Francis, 2020/05/28
- [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine, Alistair Francis, 2020/05/28
- [PATCH v5 11/11] target/riscv: Use a smaller guess size for no-MMU PMP, Alistair Francis, 2020/05/28
- [PATCH v5 08/11] hw/intc: Initial commit of lowRISC Ibex PLIC, Alistair Francis, 2020/05/28
- [PATCH v5 09/11] riscv/opentitan: Connect the PLIC device, Alistair Francis, 2020/05/28
- [PATCH v5 07/11] hw/char: Initial commit of Ibex UART, Alistair Francis, 2020/05/28
- [PATCH v5 10/11] riscv/opentitan: Connect the UART device, Alistair Francis, 2020/05/28