[RFC PATCH 8/8] riscv: Add RV64F instructions description

[LIU Zhiwei]

Signed-off-by: LIU Zhiwei <address@hidden>
---
 riscv64.risu | 78 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 78 insertions(+)

diff --git a/riscv64.risu b/riscv64.risu
index f006dc8..0b81dfb 100644
--- a/riscv64.risu
+++ b/riscv64.risu
@@ -181,4 +181,82 @@ REMW RISCV 0000001 rs2:5 rs1:5 110 rd:5 0111011 \
 REMUW RISCV 0000001 rs2:5 rs1:5 111 rd:5 0111011 \
 !constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
 
+@RV64F
 
+FLW RISCV imm:12 rs1:5 010 rd:5 0000111 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+FSW RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0000111 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 && $rs2 != 2} \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+FMADD_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1000011
+
+FMSUB_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1000111
+
+FNMSUB_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1001011
+
+FNMADD_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1001111
+
+FADD_S RISCV 0000000 rs2:5 rs1:5 rm:3 rd:5 1010011
+
+FSUB_S RISCV 0000100 rs2:5 rs1:5 rm:3 rd:5 1010011
+
+FMUL_S RISCV 0001000 rs2:5 rs1:5 rm:3 rd:5 1010011
+
+FDIV_S RISCV 0001100 rs2:5 rs1:5 rm:3 rd:5 1010011
+
+FSQRT_S RISCV 0101100 00000  rs1:5 rm:3 rd:5 1010011
+
+FSGNJ_S RISCV 0010000 rs2:5  rs1:5 000 rd:5 1010011
+
+FSGNJN_S RISCV 0010000 rs2:5  rs1:5 001 rd:5 1010011
+
+FSGNJX_S RISCV 0010000 rs2:5  rs1:5 010 rd:5 1010011
+
+FMIN_S RISCV 0010100 rs2:5  rs1:5 000 rd:5 1010011
+
+FMAX_S RISCV 0010100 rs2:5  rs1:5 001 rd:5 1010011
+
+FCVT_W_S RISCV 1100000 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FCVT_WU_S RISCV 1100000 00001 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FMV_X_W RISCV 1110000 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FEQ_S RISCV 1010000 rs2:5 rs1:5 010 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FLT_S RISCV 1010000 rs2:5 rs1:5 001 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FLE_S RISCV 1010000 rs2:5 rs1:5 000 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FCLASS_S RISCV 1110000 00000 rs1:5 001 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FCVT_S_W RISCV 1101000 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rs1 != 2 }
+
+FCVT_S_WU RISCV 1101000 00001 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rs1 != 2 }
+
+FMV_W_X RISCV 1111000 00000 rs1:5 000 rd:5 1010011 \
+!constraints { $rs1 != 2 }
+
+FCVT_L_S RISCV 1100000 00010 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
+
+FCVT_LU_S RISCV 1100000 00011 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
+
+FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
+
+FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
-- 
2.23.0