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Re: [PATCH v3 0/3] RISC-V Spike machine improvements
From: |
Alistair Francis |
Subject: |
Re: [PATCH v3 0/3] RISC-V Spike machine improvements |
Date: |
Mon, 27 Apr 2020 08:05:24 -0700 |
On Mon, Apr 27, 2020 at 1:07 AM Anup Patel <address@hidden> wrote:
>
> This series improves QEMU Spike machine to:
> 1. Allow loading OpenBI firmware using -bios option
> 2. Allow more than one CPUs
>
> Changes since v2:
> - Rebased on QEMU v5.0-rc4
>
> Changes since v1:
> - Rebased on QEMU master (commit 2ac031d171ccd18c973014d9978b4a63f0ad5fb0)
Applied to the RISC-V tree for 5.1.
Alistair
>
> Anup Patel (3):
> hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
> hw/riscv/spike: Allow loading firmware separately using -bios option
> hw/riscv/spike: Allow more than one CPUs
>
> hw/riscv/boot.c | 13 ++++++++-----
> hw/riscv/sifive_u.c | 2 +-
> hw/riscv/spike.c | 26 ++++++++++++++++++++++++--
> hw/riscv/virt.c | 2 +-
> include/hw/riscv/boot.h | 6 ++++--
> 5 files changed, 38 insertions(+), 11 deletions(-)
>
> --
> 2.25.1
>
>